5. Application Notes
5.1 Choosing the Appropriate Input Capacitor to
Optimize Slicing Level and Hum Rejection
The video designer can adjust the slicing level by choosing the value of the input
coupling capacitor. The relationship between slicing level and input coupling capacitor
is described by the following equation:
IDIS
∆VSLICE
=
∆T = VDROOP
CC
where:
IDIS = clamp discharge current = 11 μA
∆T = TLINE - TSYNC = (63.5 μs - 4.7 μs)
CC = input coupling capacitor
Figure 5-1 is a graphical representation of this equation and Figure 5-2 and Figure 5-3
show the input video waveforms for 0.1μF and 0.01μF input capacitors respectively. The
advantage in choosing a smaller input coupling capacitor, is increased hum rejection as
the following analyses illustrates.
137
127
117
107
97
87
77
0.01 0.02 0.03 0.04 0.05 0.06 0.07
0.08 0.09 0.10
INPUT COUPLING CAPACITOR (μF)
Figure 5-1: Slicing Level vs Input Coupling Capacitor
GS1881, GS4881, GS4981 Monolithic Video Sync
20 of 29
Separators
Data Sheet
Proprietary & Confidential
6926 - 5
November 2009
GENNUM [ GENNUM CORPORATION ]
