The GS1881 does not gate the Back Porch which allows for total pin compatibility with
the LM1881.
4.3 Vertical Sync Output (Pin 3)
The vertical sync interval is detected by integrating the composite sync pulses. The first
broad vertical sync pulse causes an internal capacitor to charge past a fixed threshold
and raises an internal vertical flag. Once the vertical flag is raised, the positive edge of
the next serration clocks out the vertical output. When the vertical sync interval ends,
the first post equalizing pulse is unable to charge the capacitor sufficiently, causing the
internal vertical flag to go high. The rising edge of the second post-equalizing pulse then
clocks out the high flag to end the vertical sync pulse. The vertical output is clocked in
and out and therefore is a fixed width of 197.7μs (3H + 4.7μs + 2.3μs). In the case of a
non-standard vertical interval that has no serrations, a second internal capacitor is
charged and clocks the vertical pulse out after typically 65μs. In this case the end of the
vertical pulse will still be the rising edge of the second post-equalizing pulse. As the
vertical detector is designed as a true integrator, it provides improved noise immunity.
4.4 Odd/Even Field Output (Pin 7 GS1881, GS4881)
NTSC PAL and SECAM composite video standards are interlaced video schemes and
therefore have odd and even fields. For odd fields the first broad vertical sync pulse is
coincident with the start of horizontal, while for even fields the first broad vertical sync
pulse starts in the middle of a horizontal line. Therefore by comparing the vertical sync
with an internally generated horizontal sync the odd/even field information is
determined. This output is clocked out by the falling edge of vertical sync. The odd/even
output is low during even fields and high during odd fields. This method of detecting
odd and even fields is very noise tolerant.
Noise during the pre-equalizing pulses does not affect the output since the field decision
is made at the beginning of the vertical interval. This noise immunity is displayed in
Figure 4-3 in which an extra pre-equalizing pulse has been added to the video input
with no negative effect on the odd/even field information.
Video
Input
Impulse
Noise
Even
Odd
Odd/Even
Output
Figure 4-3: Odd/Even Output
GS1881, GS4881, GS4981 Monolithic Video Sync
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Separators
Data Sheet
Proprietary & Confidential
6926 - 5
November 2009
GENNUM [ GENNUM CORPORATION ]
