GS1532 Data Sheet
Table 1-1: Pin Descriptions (Continued)
Pin
Number
13
Name
IOPROC_EN/DIS
Timing
Non
Synchronous
Type
Input
Description
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to enable or disable I/O processing features.
When set HIGH, the following I/O processing features of the device are
enabled:
• EDH Packet Generation and Insertion (SD-only)
• SMPTE 352M Packet Generation and Insertion
• ANC Data Checksum Calculation and Insertion
• Line-based CRC Generation and Insertion (HD-only)
• Line Number Generation and Insertion (HD-only)
• TRS Generation and Insertion
• Illegal Code Remapping
To enable a subset of these features, keep IOPROC_EN/DIS HIGH and
disable the individual feature(s) in the IOPROC_DISABLE register
accessible via the host interface.
When set LOW, the I/O processing features of the device are disabled,
regardless of whether the features are enabled in the IOPROC_DISABLE
register.
18
SMPTE_BYPASS
Non
Synchronous
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
When set HIGH in conjunction with DVB_ASI = LOW, the device will be
configured to operate in SMPTE mode. All I/O processing features may be
enabled in this mode.
When set LOW, the device will not support the scrambling or encoding of
received SMPTE data. No I/O processing features will be available.
19
RSET
Analog
Input
Used to set the serial digital output signal amplitude. Connect to CD_VDD
through 281Ω +/- 1% for 800mV
p-p
single-ended output swing.
Power supply connection for the serial digital cable driver. Connect to
+1.8V DC analog.
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to enable or disable the serial digital output stage.
When set LOW, the serial digital output signals SDO and SDO are
disabled and become high impedance.
When set HIGH, the serial digital output signals SDO and SDO are
enabled.
20
21
CD_VDD
SDO_EN/DIS
–
Non
Synchronous
Power
Input
22
23, 24
CD_GND
SDO, SDO
–
Analog
Power
Output
Ground connection for the serial digital cable driver. Connect to analog
GND.
Serial digital output signal operating at 1.485Gb/s, 1.485/1.001Gb/s, or
270Mb/s.
The slew rate of these outputs is automatically controlled to meet SMPTE
292M and 259M specifications according to the setting of the SD/HD pin.
21498 - 8
February 2007
7 of 51
GENNUM [ GENNUM CORPORATION ]
