GS1531 Data Sheet
4.8 Serial Digital Data PLL
To obtain a clean clock signal for serialization and transmission, the input PCLK is
locked to an external reference signal via the GS1531's integrated phase-locked
loop. This high quality analog PLL allows the GS1531 to significantly attenuate jitter
on the incoming PCLK. This PLL is also responsible for generating all internal clock
signals required by the device.
Internal division ratios for the locked PCLK are determined by the setting of the
SD/HD and 20bit/10bit pins as shown in Table 4-10.
Table 4-10: Serial Digital Output Rates
Supplied PCLK Rate
Serial Digital
Output Rate
Pin Settings
SD/HD
20bit/10bit
74.25 or
1.485 or
LOW
HIGH
74.25/1.001 MHz
1.485/1.001Gb/s
148.5 or
1.485 or
LOW
LOW
148.5/1.001MHz
1.485/1.001Gb/s
13.5MHz
27MHz
270Mb/s
270Mb/s
HIGH
HIGH
HIGH
LOW
4.8.1 External VCO
The GS1531 requires the GO1525 external voltage controlled oscillator as part of
its internal PLL.
Power for the external VCO is generated entirely by the GS1531 from an integrated
voltage regulator. The internal regulator uses +3.3V supplied on the CP_VDD /
CP_GND pins to provide +2.5V on the VCO_VCC / VCO_GND pins.
The external VCO produces a 1.485GHz reference signal for the PLL, input on the
VCO pin of the device. Both reference and control signals should be referenced to
the supplied VCO_GND as shown in the recommended application circuit of
Typical Application Circuit on page 45.
4.8.2 Lock Detect Output
The lock detect block controls the serial digital output signal and indicates to the
application layer the lock status of the device via the LOCKED output pin.
LOCKED will be asserted HIGH if and only if the internal data PLL has locked the
PCLK signal to the external VCO reference signal and one of the following is true:
1. The device is set to operate in SMPTE mode and has detected SMPTE TRS
words in the serial stream; or
2. The device is set to operate in DVB-ASI mode and has detected K28.5 sync
characters in the serial stream; or
3. The device is set to operate in Data-Through mode.
30573 - 4 July 2005
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