GF9331 Data Sheet
Table 2-2: DC Electrical Characteristics (Continued)
V
DDIO
= 3.0 to 3.6V, V
DDCORE
= 2.25 to 2.75V, T
A
= 0 to 70
o
C, unless otherwise shown.
Parameter
Tristate Leakage Current
Input Logic LOW Voltage
Input Logic HIGH Voltage
Output Logic LOW Voltage
Output Logic HIGH Voltage
I
OL
= 4mA
I
OH
= -4mA
Conditions
Symbol
I
TRILEAK
V
IL
V
IH
V
OL
V
OH
Min
-
-
2.1
-
2.7
Typ
-
-
-
0.2
-
Max
10
0.8
-
0.4
-
Units
µA
V
V
V
V
Notes
a. Production, test and QA are performed at room temperature.
Table 2-3: AC Electrical Characteristics - SDRAM Interfaces
The SDRAM 1 Interface signals include S1_CLK, S1_CS, S1_RAS, S1_CAS, S1_WE, S1_ADDR[13:0] and
S1_DAT[15:0]. The SDRAM 2 Interface signals include S2_CLK, S2_CS, S2_RAS, S2_CAS, S2_WE,
S2_ADDR[13:0] and S2_DAT[15:0].
V
DDIO
= 3.0 to 3.6V, V
DDCORE
= 2.25 to 2.75V, T
A
= 0 to 70
o
C, unless otherwise shown.
Parameter
Clock Input Frequency
Input Data Setup Time
Input Data Hold Time
Input Clock Duty Cycle
Output Data Delay Time
V
DDIO
=3.6V,
C
L
=15pF load
V
DDIO
=3.6V,
C
L
=15pF load
V
DDIO
=3.6V,
C
L
=15pF load
V
DDIO
=3.6V,
C
L
=15pF load
V
DDIO
=3.6V,
C
L
=15pF load
t
OD_SD
Conditions
Symbol
F
HSCI_SD
t
SU_SD
t
IH_SD
Min
-
2.0
2.5
40
-
Typ
85
-
-
-
-
Max
90
-
-
60
9.1
Units
MHz
ns
ns
%
ns
Notes
a
,
,
Output Data Hold Time
t
OH_SD
2.0
-
-
ns
Output Enable Time
t
OEN_SD
-
-
20
ns
,
Output Disable Time
t
ODIS_SD
-
-
20
ns
Output Data Rise/Fall Time
t
ODRF_SD
-
-
2.0
ns
,
a.Based on simulation results, verified during device characterization process.
b.50% levels.
c.Two clock cycles allocated for data bus turnaround.
d.20% to 80% levels.
Proprietary and Confidential
18303 - 4
June 2004
8 of 31
GENNUM [ GENNUM CORPORATION ]
