GL9701 PCI ExpressTM to PCI Bridge
3.4.2 Secondary PCI Interface
Name
AD[31:0]
CBE[3:0]_N
FRAME_N
IRDY_N
TRDY_N
STOP_N
DEVSEL_N
PAR
Type
TS
Description
Address/Data
TS
Command/Byte Enable
STS
STS
STS
STS
STS
TS
Secondary PCI interface frame
Secondary PCI interface initiator ready
Secondary PCI interface target ready
Secondary PCI interface stop indicator
Secondary PCI interface device select
Secondary PCI interface parity
PER_N
STS
OD
O
Secondary PCI interface parity error detect
Secondary PCI interface system error
SER_N
PCIRST_N
LOCK_N
REQ[4:0]_N
Secondary PCI bus Reset
STS
I
Secondary PCI interface target ready
Requests 4-0, activated by the secondary bus masters to request the
use of the secondary bus.
REQ0_N is a dual-purpose signal. When the bridge’s internal arbiter
is enabled, this signal is used as a request input, to be activated by a
secondary bus master requesting the use of the secondary bus. When
the internal arbiter is disabled, REQ0_N is used by the bridge as its
grant input signal.
GNT[4:0]_N
O
Grants 4-0, activated by the bridge’s internal arbiter to grant usage of
the secondary bus to the master that activated the corresponding
request signal.
GNT0_N is a dual-purpose signal. When the bridge’s internal arbiter
is enabled, this signal is used as a grant output, activated by the bridge
to grant the use of the secondary bus to the master who requested the
use with the GNT0_N signal. When the internal arbiter is disabled,
this signal is used by the bridge as its request output signal.
PCI clock input.
PCICLKI
INTA_N,
INTB_N,
INTC_N,
I
I
Interrupt from secondary interface.
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