GL811E USB 2.0 to ATA/ATAPI Bridge Controller
6.4.3 Ultra DMA data transfer
Table 6.7 - Ultra DMA data burst timing requirements
Mode 0
(in ns)
Mode 1
(in ns)
Mode 2
(in ns)
Mode 3
(in ns)
Mode 4
(in ns)
Name
Comment
min max min max min max min max Min max
Typical sustained average
two cycle time
Cycle time allowing for
asymmetry and clock
variations
Two cycle time allowing
for clock variations
Data setup time at
recipient
t2CYCTYP
tCYC
240
112
230
160
73
120
54
90
39
86
60
25
57
t2CYC
154
115
tDS
15
5
10
5
7
7
5
5
6
Data hold time at recipient
tDH
tDVS
5
5
Data valid setup time at
sender
70
48
30
20
Data valid hold time at
sender
tDVH
6
6
6
6
6
First STORBE time
tFS
tLI
0
0
230
150
0
0
200
150
0
0
170
150
0
0
130
100
0
0
120
100
Limited interlock time
Interlock time with
minimum
tMLI
tUI
20
0
20
0
20
0
20
0
20
0
Unlimited interlock time
Maximum time allowed
for output drivers to
release
tAZ
10
10
10
10
10
Minimum delay time
required for output
tZAH
20
20
20
20
20
Drivers to assert or negate
Envelope time
tZAD
tENV
0
0
0
0
0
20
70
50
20
70
30
20
70
20
20
55
20
55
STROBE to DMARDY_
time
tSR
NA
NA
Ready to final STROBE
time
Minimum time to assert
STOP or negate DMARQ
Maximum time before
releasing IORDY
Minimum time before
driving STROBE
Setup and hold times for
DMACK_
tRFS
75
70
60
60
20
60
20
tRP
160
125
100
100
100
tIORDYZ
tZIORDY
tACK
20
20
20
0
0
0
0
0
20
20
20
20
20
Time from STROBE edge
to negation of DMARQ or
assertion of STOP
tSS
50
50
50
50
50
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