GL811E USB 2.0 to ATA/ATAPI Bridge Controller
Register transfer timing parameters
Timing (ns)
t0
t1
Cycle time
2000
1000
300
900
80
Address valid to DIOR_/ DIOW_ setup
DIOR_/ DIOW_ pulse width 8-bit
DIOR_/ DIOW_ recovery time
DIOW_ data setup
t2
t2i
t3
t4
DIOW_ data hold
40
t5
DIOR_ data setup
-
t6
DIOR_ data hold
-
t6Z
t9
DIOR_ data tristate
-
DIOR_/ DIOW_ to address valid hold
900
Read Data Valid to IORDY active
(if IORDY initially low after tA)
tRD
tA
tB
tC
IORDY Setup time
-
-
-
IORDY Pulse Width
IORDY assertion to release (max)
6.4.2 Multiword DMA data transfer
Register transfer timing parameters
Cycle time
Timing (ns)
t0
tD
tE
tF
tG
tH
tI
120
80
-
DIOR_/ DIOW_ asserted pulse width
DIOR_ data access
DIOR_ data hold
-
DIOR_/ DIOW_ data setup
DIOW_ data hold
40
18
18
20
36
36
-
DMACK to DIOR_/ DIOW_ setup
DIOR_/ DIOW_ to DMACK hold
tJ
tKR DIOR_ negated pulse width
tKW DIOW_ negated pulse width
tLR DIOR_ to DMARQ delay
tLW DIOW_ to DMARQ delay
-
tM
tN
tZ
CS(1:0) (max) valid to DIOR_/ DIOW_
CS(1:0) hold
36
18
-
DMACK_ to read data released
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