MBM29LV160TE/BE-70/90/12
• Write Operation Status
Table 8 Hardware Sequence Flags
Status
DQ7
DQ7
0
DQ6
DQ5
0
DQ3
0
DQ2
1
Embedded Program Algorithm
Embedded/Erase Algorithm
Toggle
Toggle
0
1
Toggle
Erase Suspend Read
(Erase Suspended Sector)
1
1
0
Data
0
0
Data
0
Toggle
Data
In
Erase
Progress
Erase Suspend Read
Suspend
Data
DQ7
Data
(Non-Erase Suspended Sector)
Mode
Erase Suspend Program
(Non-Erase Suspended Sector)
Toggle
(Note 1)
1
(Note 2)
Embedded Program Algorithm
Embedded/Erase Algorithm
DQ7
0
Toggle
Toggle
1
1
0
1
1
Exceeded
Time
N/A
Limits
Erase Suspend Program
(Non-Erase Suspended Sector)
DQ7
Toggle
1
0
N/A
Notes: 1. Performing successive read operations from any address will cause DQ6 to toggle.
2. Reading the byte address being programmed while in the erase-suspend program mode will indicate
logic “1” at the DQ2 bit. However, successive reads from the erase-suspended sector will cause DQ2 to
toggle.
3. DQ0 and DQ1 are reserve pins for future use.
4. DQ4 is Fujitsu internal use only.
• DQ7
Data Polling
The MBM29LV160TE/BE device features Data Polling as a method to indicate to the host that the Embedded
Algorithms are in progress or completed. During the Embedded Program Algorithm, an attempt to read the
devices will produce the complement of the data last written to DQ7. Upon completion of the Embedded Program
Algorithm, an attempt to read the device will produce the true data last written to DQ7. During the Embedded
Erase Algorithm, an attempt to read the device will produce a “0” at the DQ7 output. Upon completion of the
Embedded Erase Algorithm an attempt to read the device will produce a “1” at the DQ7 output. The flowchart
for Data Polling (DQ7) is shown in Figure 22.
For chip erase and sector erase, Data Polling is valid after the rising edge of the sixth WE pulse in the six-write
pulse sequence. Data Polling must be performed at a sector address within any of the sectors being erased and
not at a protected sector. Otherwise, the status may not be valid. Once the Embedded Algorithm operation is
close to being completed, the MBM29LV160TE/BE data pins (DQ7) may change asynchronously while the output
enable (OE) is asserted low. This means that the device is driving status information on DQ7 at one instant of
time and then that byte’s valid data at the next instant of time. Depending on when the system samples the DQ7
output, it may read the status or valid data. Even if the device has completed the Embedded Program Algorithm
operation and DQ7 has a valid data, the data outputs on DQ0 to DQ6 may be still invalid. The valid data on DQ0
to DQ7 will be read on successive read attempts.
TheDataPollingfeatureisonlyactiveduringtheEmbeddedProgrammingAlgorithm, EmbeddedEraseAlgorithm
or sector erase time-out.
See Figure 9 for the Data Polling timing specifications and diagram.
22
FUJITSU [ FUJITSU ]
