MB90480/485 Series
14. Watchdog timer
The watchdog timer is a 2-bit counter that uses the output from the timebase timer or watch timer as a count
clock signal, and will reset the CPU if not cleared within a predetermined time interval after it is activated.
(1) Register List
Watchdog timer control register (WDTC)
7
6
5
4
3
2
1
0
0000A8H
Reserved
PONR
WRST
ERST
SRST
WTE
WT1
WT0
Read/write
Initial value
R
X
⎯
X
R
X
R
X
R
X
W
1
W
1
W
1
(2) Block Diagram
Watchdog timer control register (WDTC)
Watch timer control
register (WTO)
WDCS bit
Re-
PONR
WRST ERST SRST WTE WT1 WT0
served
Clock select register
(CKSCR)
SCM bit
2
Watch mode start
Timebase timer
mode start
Sleep mode start
Hold status start
CLR and
start
Watchdog timer
CLR
Counter
clear
control
circuit
Watchdog
Count
clock
Internal
reset
generator
circuit
2-bit
counter
reset
generator
circuit
selector
Stop mode
start
CLR
4
4
Clear
Time-base counter
× 21 × 22
× 28 × 29 × 210 × 211 × 212 × 213 × 214 × 215 × 216 × 217 × 218
HCLK × 2
SCLK
× 21 × 22
× 28 × 29 × 210 × 211 × 212 × 213 × 214 × 215 × 216 × 217 × 218
HCLK : Oscillator clock
SCLK : Sub clock
66
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