MB90480/485 Series
(8) Hold Timing
(VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = − 40 °C to +85 °C)
Value
Parameter
Symbol Pin name Conditions
Unit
Remarks
Min
30
Max
tCP*
Pin floating→HAK↓time
HAK↓→pin valid time
tXHAL
tHAHV
HAK
HAK
ns
ns
⎯
tCP*
2 tCP*
* : tCP is internal operating clock cycle time. Refer to “ (1) Clock Timing”.
Note : One or more cycles are required from the time the HRQ pin is read until the HAK signal changes.
HAK
2.4 V
0.8 V
tXHAL
tHAHV
High-Z
2.4 V
0.8 V
2.4 V
0.8 V
Pins
(9) UART Timing
(VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Pin
Parameter
Serial clock cycle time
SCK↓→SOT delay time
Symbol
tSCYC
Conditions
Unit Remarks
name
Min
8 tCP*2
−80
−120
100
200
tCP*2
4 tCP*2
4 tCP*2
⎯
Max
⎯
⎯
ns
+80
+120
⎯
ns
tSLOV
⎯
⎯
Internal shift clock
mode output pins :
CL*1 = 80 pF + 1 TTL
ns fCP = 8 MHz
ns
Valid SIN→SCK↑
tIVSH
⎯
ns fCP = 8 MHz
SCK↑→valid SIN hold time
Serial clock “H” pulse width
Serial clock “L” pulse width
tSHIX
tSHSL
tSLSH
⎯
⎯
⎯
⎯
ns
⎯
ns
⎯
ns
150
200
⎯
ns
SCK↓→SOT delay time
Valid SIN→SCK↑
tSLOV
tIVSH
tSHIX
⎯
⎯
⎯
External shift clock
mode output pins :
CL*1 = 80 pF + 1 TTL
⎯
ns fCP = 8 MHz
ns
60
120
60
⎯
ns fCP = 8 MHz
ns
⎯
SCK↑→valid SIN hold time
120
⎯
ns fCP = 8 MHz
*1 : CL is the load capacitance applied to pins for testing.
*2 : tCP is internal operating clock cycle time. Refer to “ (1) Clock Timing”.
Note : The above rating is in CLK synchronous mode.
100
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