欢迎访问ic37.com |
会员登录 免费注册
发布采购

MB15F72SP 参数 Datasheet PDF下载

MB15F72SP图片预览
型号: MB15F72SP
PDF下载: 下载PDF文件 查看货源
内容描述: 双串行输入锁相环频率合成器 [Dual Serial Input PLL Frequency Synthesizer]
分类和应用:
文件页数/大小: 27 页 / 272 K
品牌: FUJITSU [ FUJITSU ]
 浏览型号MB15F72SP的Datasheet PDF文件第9页浏览型号MB15F72SP的Datasheet PDF文件第10页浏览型号MB15F72SP的Datasheet PDF文件第11页浏览型号MB15F72SP的Datasheet PDF文件第12页浏览型号MB15F72SP的Datasheet PDF文件第14页浏览型号MB15F72SP的Datasheet PDF文件第15页浏览型号MB15F72SP的Datasheet PDF文件第16页浏览型号MB15F72SP的Datasheet PDF文件第17页  
MB15F72SP  
PHASE COMPARATOR OUTPUT WAVEFORM  
frIF/frRF  
fpIF/fpRF  
tWU  
tWL  
LD  
(FC bit = “1”)  
H
DoIF/DoRF  
Z
L
(FC bit = “0”)  
H
DoIF/DoRF  
Z
L
• LD Output Logic  
IF-PLL section  
RF-PLL section  
Locking state/Power saving state  
Unlocking state  
LD output  
Locking state/Power saving state  
Locking state/Power saving state  
Unlocking state  
H
L
L
L
Locking state/Power saving state  
Unlocking state  
Unlocking state  
Notes:Phase error detection range = –2π to +2π  
Pulses on DoIF/DoRF signals are output to prevent dead zone during locking state.  
LD output becomes low when phase error is tWU or more.  
LD output becomes high when phase error is tWL or less and continues to be so for three cycles or more.  
tWU and tWL depend on OSCIN input frequency as follows.  
tWU > 2/fosc : e.g. tWU > 156.3 ns when fosc = 12.8 MHz  
tWU < 4/fosc : e.g. tWL < 312.5 ns when fosc = 12.8 MHz  
13