MB15F72SP
■ PHASE COMPARATOR OUTPUT WAVEFORM
frIF/frRF
fpIF/fpRF
tWU
tWL
LD
(FC bit = “1”)
H
DoIF/DoRF
Z
L
(FC bit = “0”)
H
DoIF/DoRF
Z
L
• LD Output Logic
IF-PLL section
RF-PLL section
Locking state/Power saving state
Unlocking state
LD output
Locking state/Power saving state
Locking state/Power saving state
Unlocking state
H
L
L
L
Locking state/Power saving state
Unlocking state
Unlocking state
Notes:•Phase error detection range = –2π to +2π
•Pulses on DoIF/DoRF signals are output to prevent dead zone during locking state.
•LD output becomes low when phase error is tWU or more.
•LD output becomes high when phase error is tWL or less and continues to be so for three cycles or more.
•tWU and tWL depend on OSCIN input frequency as follows.
tWU > 2/fosc : e.g. tWU > 156.3 ns when fosc = 12.8 MHz
tWU < 4/fosc : e.g. tWL < 312.5 ns when fosc = 12.8 MHz
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FUJITSU [ FUJITSU ]
