MB1504
MB1504H
MB1504L
FUNCTIONAL DESCRIPTIONS
PROGRAMMABLE DIVIDER
The programmable divider consists of a 19-bit shift register, 18-bit latch, 7-bit swallow counter and 11-bit programmable counter.
Serial 19-bit data format is shown below.
Data input
Last data input
First data input
Control bit
LSB
MSB
S
1
S
2
S
3
S
4
S
5
S
6
S
7
S
8
S
9
S
S
S
S
S
S
S
S
S
C
10
11
12
13
14
15
16
17
18
Divide ratio of swallow counter
setting bits
Divide ratio of programmable counter
setting bits
7-BIT SWALLOW COUNTER DIVIDE RATIO
11-BIT PROGRAMMABLE COUNTER DIVIDE RATIO
Divide
Divide
ratio
A
S
S
S
S
S
S
S
S
S
S
9
S
8
S
7
S
6
S
5
S
4
S
3
S
2
S
1
ratio
N
18
17
16
15
14
13
12
11
0
10
16
17
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
1
1
•
0
0
•
0
0
•
0
1
•
0
1
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
1
•
0
•
•
•
2047
1
1
1
1
63
0
1
1
1
1
1
1
1
1
1
1
1
1
1
Divide ratio less than 16 is prohibited
Divide ratio N : 16 to 2047
Divide ratio A : 0 to 63
S to S
1
:
:
Divide ratio of programmable counter setting bits (16 to 2047)
Divide ratio of swallow counter setting bits (0 to 127)
8
18
7
S to S
C: Control bit (control bit is set to low)
Data is input from the MSB.
6
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