MB95120MB Series
(VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = −40 °C to + 105 °C)
Value*2
Sym- Pin
bol name
Parameter
Condition
Unit
Remarks
Min
Max
SCL clock
“L” width
tLOW SCL0
tHIGH SCL0
(2 + nm / 2) tMCLK − 20
⎯
ns Master mode
SCL clock
“H” width
(nm / 2) tMCLK − 20
(nm / 2 ) tMCLK + 20
ns Master mode
Master mode
Maximum value is
applied when m,
ns n = 1, 8.
Start condition
hold time
SCL0
tHD;STA
(−1 + nm / 2) tMCLK − 20
(−1 + nm) tMCLK + 20
SDA0
Otherwise, the
minimum value is
applied.
Stop condition
setup time
SCL0
tSU;STO
(1 + nm / 2) tMCLK − 20 (1 + nm / 2) tMCLK + 20
(1 + nm / 2) tMCLK − 20 (1 + nm / 2) tMCLK + 20
ns Master mode
ns Master mode
SDA0
Start condition
setup time
SCL0
tSU;STA
SDA0
Bus free time
between stop
condition and
start condition
SCL0
tBUF
(2 nm + 4) tMCLK − 20
3 tMCLK − 20
⎯
⎯
ns
SDA0
SCL0
SDA0
Data hold time tHD;DAT
ns Master mode
Master mode
When assuming
that “L” of SCL is
not extended, the
minimum value is
ns applied to first bit
of continuous
R = 1.7 kΩ,
C = 50 pF*1
Data setup
tSU;DAT
SCL0
SDA0
(−2 + nm / 2) tMCLK − 20 (−1 + nm / 2) tMCLK + 20
time
data.
Otherwise,
the maximum
value is applied.
Minimum value is
appliedtointerrupt
at 9th SCL↓.
Maximum value is
appliedtointerrupt
at 8th SCL↓.
Setup time
between
clearing
interrupt and
SCL rising
(nm / 2) tMCLK − 20
(1 + nm / 2) tMCLK + 20
tSU;INT SCL0
ns
SCL clock “L”
width
4 tMCLK − 20
4 tMCLK − 20
tLOW SCL0
tHIGH SCL0
⎯
⎯
ns At reception
ns At reception
SCL clock “H”
width
Undetected when
ns 1 tMCLK is used at
reception
Start condition
detection
SCL0
tHD;STA
2 tMCLK − 20
⎯
SDA0
(Continued)
59
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