MB95120MB Series
Sampling at the rising edge of sampling clock*1 and enabled serial clock delay*2
(ESCR register : SCES bit = 0, ECCR register : SCDE bit = 1)
(VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = −40 °C to + 105 °C)
Value
Sym-
bol
Parameter
Pin name
Condition
Unit
Min
Max
⎯
Serial clock cycle time
SCK ↑ → SOT delay time
Valid SIN → SCK ↓
tSCYC
tSHOVI
tIVSLI
SCK
5 tMCLK*3
ns
ns
ns
ns
ns
SCK, SOT
−95
+95
⎯
Internal clock
SCK, SIN operation output pin : tMCLK*3 + 190
CL = 80 pF + 1 TTL.
SCK ↓ → valid SIN hold time
SOT → SCK ↓ delay time
tSLIXI
SCK, SIN
SCK, SOT
0
⎯
4 tMCLK*3
tSOVLI
⎯
*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the
serial clock.
*2 : Serial clock delay function is used to delay half clock for the output signal of serial clock.
*3 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
t
SCYC
2.4 V
SCK
0.8 V
0.8 V
t
SHOVI
t
SOVLI
2.4 V
0.8 V
2.4 V
0.8 V
SOT
SIN
tSLIXI
tIVSLI
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
55
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