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EDC4BV7244-70TG-S 参数 Datasheet PDF下载

EDC4BV7244-70TG-S图片预览
型号: EDC4BV7244-70TG-S
PDF下载: 下载PDF文件 查看货源
内容描述: [Memory IC, 4MX72, CMOS, PDMA168]
分类和应用: 光电二极管
文件页数/大小: 8 页 / 134 K
品牌: FUJITSU [ FUJITSU COMPONENT LIMITED. ]
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November 1996
Revision 1.0
EDC4BV724(2/4)-(60/70)(J/T)G-S
Functional Diagram
RAS0*
CAS0*
WE0*
OE0*
A0
DQ0~DQ35
RAS2*
4M x 36
BLOCK
CAS4*
WE2*
OE2*
B0
DQ36~DQ71
4M x 36
BLOCK
DQ0~DQ71
Notes: 1.
2.
3.
4.
5.
All signals including PDs (with the exception of RAS*, data and
IDs) are buffered.
*
” signifies active low signal.
Addresses A1~A10/A11 (A11 is NC for 2K Refresh modules) are
connected to all devices.
Each 4Mx36 Block comprises of nine 4Mx4 EDO devices.
All specifications of this device are subject to change without
notice.
V
CC
V
SS
Decoupling capacitors
to all devices
2
Fujitsu Microelectronics, Inc.