November 1996
Revision 1.0
EDC4BV724(2/4)-(60/70)(J/T)G-S
Functional Diagram
RAS0*
CAS0*
WE0*
OE0*
A0
DQ0~DQ35
RAS2*
4M x 36
BLOCK
CAS4*
WE2*
OE2*
B0
DQ36~DQ71
4M x 36
BLOCK
DQ0~DQ71
Notes: 1.
2.
3.
4.
5.
All signals including PDs (with the exception of RAS*, data and
IDs) are buffered.
“
*
” signifies active low signal.
Addresses A1~A10/A11 (A11 is NC for 2K Refresh modules) are
connected to all devices.
Each 4Mx36 Block comprises of nine 4Mx4 EDO devices.
All specifications of this device are subject to change without
notice.
V
CC
V
SS
Decoupling capacitors
to all devices
2
Fujitsu Microelectronics, Inc.