CS402 Series
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DESIGN METHODS
Fujitsu Semiconductor's Reference Design Flow provides the following functions that help reduce the devel-
opment time of large scale, high quality LSIs.
• Statistical Static Timing Analysis (SSTA) improves timing convergence.
• Physical Prototyping enables more accurate estimation of highly reliable designs.
• Layout synthesis with optimized timing is realized by Physical Synthesis Tool.
• High accuracy design environment where voltage drop of power supply, signal noise, delay penalty and
crosstalk are considered
• I/O design environment (power line design, assignment and selection of I/Os, package selection) where
noise is considered
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PACKAGES
The CS402 series can use the same packages that are available for the previous series, allowing a smooth
transition from previously developed models. For details of delivery times, contact the sales representative.
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FBGA packages
PBGA packages
TEBGA packages
FC-BGA packages
DS601-00002-0v01-E
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FUJITSU [ FUJITSU COMPONENT LIMITED. ]
