欢迎访问ic37.com |
会员登录 免费注册
发布采购

CS402 参数 Datasheet PDF下载

CS402图片预览
型号: CS402
PDF下载: 下载PDF文件 查看货源
内容描述: 富士通半导体数据表 [FUJITSU SEMICONDUCTOR DATA SHEET]
分类和应用: 半导体
文件页数/大小: 8 页 / 83 K
品牌: FUJITSU [ FUJITSU COMPONENT LIMITED. ]
 浏览型号CS402的Datasheet PDF文件第2页浏览型号CS402的Datasheet PDF文件第3页浏览型号CS402的Datasheet PDF文件第4页浏览型号CS402的Datasheet PDF文件第5页浏览型号CS402的Datasheet PDF文件第6页浏览型号CS402的Datasheet PDF文件第7页浏览型号CS402的Datasheet PDF文件第8页  
FUJITSU SEMICONDUCTOR
DATA SHEET
DS601-00002-0v01-E
Semicustom
CMOS
Standard Cell
CS402 Series
DESCRIPTION
The CS402 series of 28 nm standard cells is a line of CMOS ASICs of high-performance with minimum
power consumption.
By the adoption of core transistors with high current drivability operating at low voltages, the operating
frequency approximately twice that of CS401 series is realized at power supply voltages 10% lower than
those of CS401 series.
This series is appropriate for high-performance/high-end applications ranging from the engines of handheld
terminals to telecommunication equipment.
FEATURES
• Technology
: 28 nm Metal-gate CMOS
: Maximum 11-metal layers. Ultra low permittivity material is used for inter-layer dielectric.
: Core transistors with different threshold voltages can be used on the same chip
(ultra low leak, low leak, standard, high speed and ultra high speed).
Supply voltage : Internal power supply :
+
0.9 V
±
0.09 V
: External power supply :
+
1.8 V
±
0.15 V
(1.8V interface on dual-power supply system)
Junction temperature range:
40
°C
to
+
125
°C
(Standard specification)
Operating frequency: Approximately twice that of CS401 series
Support various types of high-quality cell sets developed by FUJITSU SEMICONDUCTOR (from low power
versions to high speed versions).
Support SRAMs with standby-mode and power-down mode for lower power consumption memories.
Compiled cells (RAM, ROM, others)
Support special interfaces (LVDS, SSTL, others).
Support boundary SCAN test.
Support use of industry standard libraries.
Support use of industry standard tools.
Short-term development using a physical prototyping tool
One-pass design using a physical synthesis tool
Hierarchical design environment for supporting large-scale circuits
Support Signal Integrity, EMI noise reduction.
Support static timing sign-off.
Improve timing convergence by the introduction of Statistical Static Timing Analysis (SSTA).
Design For Manufacturing (DFM) enables stable product-supply and reduced variation.
Package lineup: FBGA, PBGA, TEBGA, FC-BGA
Note: Including items under development.
Copyright©2012 FUJITSU SEMICONDUCTOR LIMITED All rights reserved
2012.6