D A T A S H E E T
AC CHARACTERISTICS
555 for program
PA for program
2AA for erase
SA for sector erase
555 for chip erase
Data# Polling
Addresses
PA
tWC
tWH
tAS
tAH
WE#
OE#
tGHEL
tWHWH1 or 2
tCP
CE#
Data
tWS
tCPH
tDS
tDH
DQ7#
DOUT
A0 for program
55 for erase
PD for program
30 for sector erase
10 for chip erase
Notes:
1. PA is the address of the memory location to be programmed.
2. PD is the data to be programmed at address PA.
3. DQ7 is the complement of the data written to the device.
4. DOUT is the data written to the device.
5. Figure indicates the last two bus cycles of the command sequence.
Figure 17. Alternate CE# Controlled Write Operation Timings
ERASE AND PROGRAMMING PERFORMANCE
Parameter
Typ (Note 1)
Max (Note 3)
Unit
s
Comments
Sector Erase Time
0.7
6
15
Excludes 00h programming
prior to erasure (Note 4)
Chip Erase Time (Note 2)
Byte Programming Time
Chip Programming Time (Note 2)
s
9
300
3.3
µs
s
Excludes system level
overhead (Note 5)
1.1
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 3.0 V VCC, 1,000,000 cycles. Additionally,
programming typicals assume checkerboard pattern.
2. Under worst case conditions of 90°C, VCC = 2.7 V, 1,000,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum program times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See
Table 4 for further information on command definitions.
6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles.
32
Am29LV010B
22140D6 October 11, 2006
FUJITSU [ FUJITSU ]
