D A T A S H E E T
AC CHARACTERISTICS
Read Operations
Parameter
Speed Options
JEDEC
Std
Description
Test Setup
-55
-70
-90
Unit
tAVAV
tRC
Read Cycle Time (Note 1)
Min
55
55
70
90
90
ns
CE# = VIL
OE# = VIL
tAVQV
tACC Address to Output Delay
Max
70
ns
tELQV
tGLQV
tEHQZ
tGHQZ
tCE
tOE
tDF
tDF
Chip Enable to Output Delay
Output Enable to Output Delay
OE# = VIL
Max
Max
Max
Max
Min
55
30
15
15
70
30
25
25
0
90
35
30
30
ns
ns
ns
ns
ns
Chip Enable to Output High Z (Note 1)
Output Enable to Output High Z (Note 1)
Read
Output Enable
Hold Time (Note 1)
tOEH
Toggle and
Data# Polling
Min
Min
10
0
ns
ns
Output Hold Time From Addresses, CE# or OE#,
Whichever Occurs First (Note 1)
tAXQX
tOH
Notes:
1. Not 100% tested.
2. See Figure 9 and Table 6 for test specifications.
tRC
Addresses Stable
tACC
Addresses
CE#
tDF
tOE
OE#
tOEH
WE#
tCE
tOH
HIGH Z
HIGH Z
Output Valid
Outputs
Figure 11. Read Operations Timings
26
Am29LV010B
22140D6 October 11, 2006
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