D A T A S H E E T
TEST CONDITIONS
Table 6. Test Specifications
-70,
3.3 V
Test Condition
-55
-90
Unit
2.7 kΩ
Output Load
1 TTL gate
Device
Under
Test
Output Load Capacitance, CL
(including jig capacitance)
30
100
pF
C
L
6.2 kΩ
Input Rise and Fall Times
Input Pulse Levels
5
0.0–3.0
ns
V
Input timing measurement
reference levels
1.5
1.5
V
V
Note:Diodes are IN3064 or equivalent
Output timing measurement
reference levels
Figure 9. Test Setup
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Does Not Apply
Changing, State Unknown
Center Line is High Impedance State (High Z)
3.0 V
0.0 V
1.5 V
1.5 V
Input
Measurement Level
Output
Figure 10. Input Waveforms and Measurement Levels
October 11, 2006 22140D6
Am29LV010B
25
FUJITSU [ FUJITSU ]
