D A T A S H E E T
Table 3. In addition, when verifying sector protection,
Autoselect Mode
the sector address must appear on the appropriate
highest order address bits (see Table 2). When all nec-
essary bits have been set as required, the
programming equipment may then read the corre-
sponding identifier code on DQ7-DQ0.
The autoselect mode provides manufacturer and
device identification, and sector protection verification,
through identifier codes output on DQ7–DQ0. This
mode is primarily intended for programming equipment
to automatically match a device to be programmed with
its corresponding programming algorithm. However,
the autoselect codes can also be accessed in-system
through the command register.
To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in Table 4. This method
does not require V . See “Command Definitions” for
details on using the autoselect mode.
ID
When using programming equipment, the autoselect
mode requires V (11.5 V to 12.5 V) on address pin
ID
A9. Address pins A6, A1, and A0 must be as shown in
Table 3. Am29LV010B Autoselect Codes
A16 A13
to to
OE# WE# A14 A10 A9
A8
to
A7
A5
to
A2
DQ7
to
DQ0
Description
Manufacturer ID: AMD
Device ID: Am29LV010B
CE#
L
A6
L
A1
L
A0
L
L
L
H
H
X
X
X
X
VID
VID
X
X
X
X
01h
6Eh
L
L
L
H
01h
(protected)
Sector Protection Verification
L
L
H
SA
X
VID
X
L
X
H
L
00h
(unprotected)
L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.
command definitions). In addition, the following hard-
ware data protection measures prevent accidental
erasure or programming, which might otherwise be
Sector Protection/Unprotection
The hardware sector protection feature disables both
program and erase operations in any sector. The hard-
ware sector unprotection feature re-enables both
program and erase operations in previously protected
sectors.
caused by spurious system level signals during V
CC
power-up and power-down transitions, or from system
noise.
Low V
Write Inhibit
CC
The method intended only for programming equipment
When V
is less than V
, the device does not
LKO
requires V on address pin A9, and OE#. This method
CC
ID
accept any write cycles. This protects data during V
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until V
is greater than V
is compatible with programmer routines written for
earlier 3.0 volt-only AMD flash devices. Publication
number 22134 contains further details; contact an
AMD representative to request a copy.
CC
CC
. The system must provide the
LKO
The device is shipped with all sectors unprotected.
AMD offers the option of programming and protecting
sectors at its factory prior to shipping the device
through AMD’s ExpressFlash™ Service. Contact an
AMD representative for details.
proper signals to the control pins to prevent uninten-
tional writes when V is greater than V
.
CC
LKO
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
It is possible to determine whether a sector is protected
or unprotected. See “Autoselect Mode” for details.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
Hardware Data Protection
V , CE# = V or WE# = V . To initiate a write cycle,
IL
IH
IH
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to Table 4 for
CE# and WE# must be a logical zero while OE# is a
logical one.
12
Am29LV010B
22140D6 October 11, 2006
FUJITSU [ FUJITSU ]
