D A T A S H E E T
system can then read autoselect codes from the but not within V
± 0.3 V, the device will be in the
CC
internal register (which is separate from the memory
array) on DQ7–DQ0. Standard read cycle timings apply
in this mode. Refer to the Autoselect Mode and Autose-
lect Command Sequence sections for more
information.
standby mode, but the standby current will be greater.
The device requires standard access time (t ) for read
CE
access when the device is in either of these standby
modes, before it is ready to read data.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
I
in the DC Characteristics table represents the
CC2
active current specification for the write mode. The “AC
Characteristics” section contains timing specification
tables and timing diagrams for write operations.
I
in the DC Characteristics table represents the
CC3
standby current specification.
Program and Erase Operation Status
During an erase or program operation, the system may
check the status of the operation by reading the status
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device
energy consumption. The device automatically enables
bits on DQ7–DQ0. Standard read cycle timings and I
CC
this mode when addresses remain stable for t
+ 30
ACC
read specifications apply. Refer to “Write Operation
Status” for more information, and to “AC Characteris-
tics” for timing diagrams.
ns. The automatic sleep mode is independent of the
CE#, WE#, and OE# control signals. Standard address
access timings provide new data when addresses are
changed. While in sleep mode, output data is latched
Standby Mode
and always available to the system. I
in the DC
CC4
When the system is not reading or writing to the device,
it can place the device in the standby mode. In this
mode, current consumption is greatly reduced, and the
outputs are placed in the high impedance state, inde-
pendent of the OE# input.
Characteristics table represents the automatic sleep
mode current specification.
Output Disable Mode
When the OE# input is at V , output from the device is
IH
The device enters the CMOS standby mode when the
disabled. The output pins are placed in the high imped-
ance state.
CE# pin is held at V ± 0.3 V. (Note that this is a more
CC
restricted voltage range than V .) If CE# is held at V ,
IH
IH
Table 2. Am29LV010B Uniform Sector Address Table
Sector
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
A16
0
A15
0
A14
0
Address Range
00000h-03FFFh
04000h-07FFFh
08000h-0BFFFh
0C000h-0FFFFh
10000h-13FFFh
14000h-17FFFh
18000h-1BFFFh
1C000h-1FFFFh
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
October 11, 2006 22140D6
Am29LV010B
11
FUJITSU [ FUJITSU ]
