MBM29F800TA-55/-70/-90/MBM29F800BA-55/-70/-90
■ AC CHARACTERISTICS
• Read Only Operations Characteristics
Parameter
MBM29F800TA/BA
Symbols
Description
Test Setup
Unit
-55
-70
-90
JEDEC Standard
(Note1) (Note2) (Note2)
tAVAV
tAVQV
tRC
Read Cycle Time
—
Min.
Max.
55
55
70
70
90
90
ns
ns
CE = VIL
OE = VIL
tACC
Address to Output Delay
tELQV
tGLQV
tEHQZ
tGHQZ
tCE
tOE
tDF
tDF
Chip Enable to Output Delay
Output Enable to Output Delay
Chip Enable to Output High-Z
Output Enable to Output High-Z
OE = VIL Max.
55
30
15
15
70
30
20
20
90
40
20
20
ns
ns
ns
ns
—
—
—
Max.
Max.
Max.
Output Hold Time From
Addresses, CE or OE, Whichever
Occurs First
tAXQX
tOH
—
Min.
0
0
0
ns
—
—
tREADY
RESET Pin Low to Read Mode
—
—
Max.
Max.
20
5
20
5
20
5
µs
tELFL
tELFH
CE or BYTE Switching Low or
High
ns
Note: 2. Test Conditions:
Note: 1. Test Conditions:
Output Load: 1 TTL gate and 30 pF
Output Load: 1 TTL gate and 100 pF
Input rise and fall times: 5 ns
Input pulse levels: 0.45 V to 2.4 V
Timing measurement reference level
Input: 0.8 V and 2.0 V
Input rise and fall times: 5 ns
Input pulse levels: 0.0 V to 3.0 V
Timing measurement reference level
Input: 1.5 V
Output: 0.8 V and 2.0 V
Output: 1.5 V
5.0 V
IN3064
or Equivalent
2.7 kΩ
Device
Under
Test
6.2 kΩ
CL
Diodes = IN3064
or Equivalent
Notes: 1. CL = 30 pF including jig capacitance (MBM29F800TA/BA-55)
2. CL = 100 pF including jig capacitance (MBM29F800TA/BA-70/-90)
Figure 4 Test Conditions
26
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