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29F800 参数 Datasheet PDF下载

29F800图片预览
型号: 29F800
PDF下载: 下载PDF文件 查看货源
内容描述: 8M ( 1M ×8 / 512K ×16 )位 [8M (1M X 8/512K X 16) BIT]
分类和应用:
文件页数/大小: 48 页 / 516 K
品牌: FUJITSU [ FUJITSU ]
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MBM29F800TA-55/-70/-90/MBM29F800BA-55/-70/-90  
The DQ5 failure condition may also appear if a user tries to program a non blank location without erasing. In this  
case the device locks out and never complete the Embedded Algorithm operation. Hence, the system never  
reads a valid data on DQ7 bit and DQ6 never stops toggling. Once the device has exceeded timing limits, the  
DQ5 bit will indicate a “1.” Please note that this is not a device failure condition since the device was incorrectly  
used. If this occurs, rest the device with command sequence.  
DQ3  
Sector Erase Timer  
After the completion of the initial sector erase command sequence the sector erase time-out will begin. DQ3 will  
remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial sector erase  
command sequence.  
If Data Polling or the Toggle Bit I indicates the device has been written with a valid erase command, DQ3 may  
be used to determine if the sector erase timer window is still open. If DQ3 is high (“1”) the internally controlled  
erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase  
operation is completed as indicated by Data Polling or Toggle Bit I. If DQ3 is low (“0”), the device will accept  
additional sector erase commands. To insure the command has been accepted, the system software should  
check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 were high on the  
second status check, the command may not have been accepted.  
Refer to Table 8: Hardware Sequence Flags.  
DQ2  
Toggle Bit II  
This toggle bit II, along with DQ6, can be used to determine whether the device is in the Embedded Erase  
Algorithm or in Erase Suspend.  
Successive reads from the erasing sector will cause DQ2 to toggle during the Embedded Erase Algorithm. If the  
device is in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause DQ2  
to toggle. When the device is in the erase-suspended-program mode, successive reads from the byte address  
of the non-erase suspended sector will indicate a logic “1” at the DQ2 bit.  
DQ6 is different from DQ2 in that DQ6 toggles only when the standard program or Erase, or Erase Suspend  
Program operation is in progress. The behavior of these two status bits, along with that of DQ7, is summarized  
as follows:  
Mode  
DQ7  
DQ7  
0
DQ6  
DQ2  
1
Program  
Erase  
toggles  
toggles  
toggles  
Erase Suspend Read  
(Erase-Suspended Sector)  
(Note 1)  
1
1
toggles  
Erase Suspend Program  
DQ7 (Note 2)  
toggles  
1 (Note 2)  
Notes: 1. These status flags apply when outputs are read from a sector that has been erase-suspended.  
2. Thesestatusflagsapplywhenoutputsarereadfromthebyteaddressofthenon-erasesuspendedsector.  
For example, DQ2 and DQ6 can be used together to determine the erase-suspend-read mode (DQ2 toggles while  
DQ6 does not). See also Table 8 and Figure 22.  
Furthermore, DQ2 can also be used to determine which sector is being erased. When the device is in the erase  
mode, DQ2 toggles if this bit is read from the erasing sector.  
20  
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