FA5502P/M
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(4) Output overvoltage at light load
A compensation circuit for light load is incorporated
for preventing an overvoltage when light or no load.
Though, according to the condition, this circuit may not
compensate enough and overvoltage may occur. To
prevent overvoltage, the following condition must be
satisfied.
(6) Improvement of output voltage regulation
As stated in “9-(5)”, the output voltage may change
with input voltage or load current on the circuit in Fig.6
in "8-(2)", thereby causing a problem in some case. In
such a case, the circuit in Fig.24 may improve the
regulation.
Vo
- Noise filter resistor Rn connected to IDET pin (pin
16) must be below 27Ω.
- As shown in Fig.22, DC gain limiting resistor R10
for current error amplifier must not be connected
between IFB pin (pin 1) and IIN- pin (pin 2).
R13
VFB
VIN-
5
6
C8
R2
R1
MUL
R3
C9
R5 C2
2
IIN-
Vr
=1.55V(typ.)
R10
FA5502
1
IFB
C3
Fig.24 ER.AMP circuit for improvement of regulation
Fig.22 Prevention of overvoltage at light load
Voltage gainAv2 of this circuit is expressed by:
(5) Notes for setting the output voltage and
overvoltage limit
1+ jωC9×R13
jω((C8 + C9) + jωC8×C9×R13)R3
AV2
=
• • • (18)
In the actual circuit, the output voltage drops
depending on the line voltage or load current.
Therefore, the output voltage may be lower than the
voltage calculated by expression (1) in "8-(2)". When
setting the output voltage, sufficiently evaluate it on an
actual circuit.
Optimum values depend on an each circuit.
Referring the following relations or the example
applied to “10 Example of application circuit”, adjust
the values on actual circuit.
On the circuit shown in Fig.6 in "8-(2)", the
overvoltage setting is fixed at 1.058 times the output
voltage setting.
- Set the voltage gain Av2 at 100 or 120 Hz almost
the same as before changing the compensation
circuit.
For setting the overvoltage independently of the
output voltage setting, connect voltage divider
additionally to OVP pin as shown in Fig.23.
- Determine C8, C9 and R13 so as to satisfy the
following relations.
On the circuit in Fig.23, even if the voltage divider
for setting the output voltage has troubled, the
overvoltage limiting circuit operates properly, thereby
preventing the output voltage from rising excessively.
• Set fz determined by the following expression to
several Hz to several ten Hz.
1
fZ
=
• • • • • (19)
2πC9× R13
Vo
• Set fp determined by the following expression so
that the fp/fz ratio is about 10.
C1
VFB
VIN-
5
6
1
C8×C9
C8 + C9
R2
R1
fp =
C =
• • • • • (20)
R4
R3
ER.AMP
Vr
2πC×R13
MUL
F.F.
*Example of values applied to “10 Example of
application circuit”
C8=0.033µF, C9=0.15µF,
R13=330kΩ, R3=100kΩ
(These values are given as references and not
intended for guaranteeing the operation in any
circuit.)
=1.55V(typ.)
R12
R11
OVP.COMP
OVP
4
In this circuit, not only the output voltage
characteristics at a steady status but also transient
response to line voltage and load current may change.
Before determining the circuit values, evaluate
sufficiently.
Vp
=1.058Vr(typ.)
Fig.23 Independent setting of OVP limit
20
FUJI [ FUJI ELECTRIC ]
