FA5502P/M
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Normal operation
VIFB
V
CT
CS
V
G1
t
t
OUT
pin
Z
P
frequency
Fig.8 Voltage gain of CUR.AMP
Operation with Dmax
(4) PWM comparator
V
VCIFSB
Fig.9 shows the configuration of PWM comparator.
Oscillator output VCT and current error amplifier output
V
CT
VIFB are compared. While VCT
<
VIFB, PWM
comparator output goes High and OUT pin also goes
High. Note that, during the oscillator discharge period,
OUT pin is forced to be Low, thereby determining the
maximum duty cycle. (see characteristics curve).
t
t
OUT
pin
CS pin (pin 11) is a soft start pin. When start up, an
internal constant current (11µA (typ.)) charges
capacitor C4 for soft start. Priority is given to VCS or
VIFB whichever is lower. Fig.10 shows PWM
comparator timing chart.
Fig.10 PWM comparator timing chart
(5) Multiplier
The multiplier generates a current reference signal.
The rectified line voltage is divided down by resistor
and monitored by VDET pin (pin 3). Considering the
dynamic range of multiplier, design the R6 and R7 in
Fig.11 so that the peak voltage at VDET pin within a
range from 0.65V to 2.4V over the entire range of line
voltage. VFB pin is normally above 1.55V and, at this
status, multiplier output voltage Vm is approximately
expressed by:
CUR.AMP output
V
V
IFB
CT
(IFB pin)
Oscillator output
(CT pin)
Output
circuit
CS
V
CS
11
PWM.COMP
11µA
Vm = 1.25 −K ×(VVFB −1.55)× VVDET • • • • • (8)
C4
7.5V
Where
K: Output voltage factor (multiplier section)
Fig.9 PWM comparator circuit
When VFB pin is lower than 1.55V, compensation
circuit for light load operates.
As shown in Fig.7, Vm is applied via a resistor of
11 kΩ to inverting input (IIN-) of current error amplifier
CUR. AMP. (For input/output characteristics of
multiplier, see characteristics curve.)
VIN
VVFB
ER.AMP output
(VFB pin)
R7
R6
VDET
V
MUL
3
Vm
VDET
Fig.11 Multiplier circuit
15
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