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Document No.: FT_000138

VINCULUM-II EMBEDDED DUAL USB HOST CONTROLLER IC Datasheet

Version -

1.0

Clearance No.: FTDI#

143

6.7 Parallel FIFO – Synchronous Mode

The Parallel FIFO Synchronous mode has an eight bit data bus, individual read and write strobes, two

hardware flow control signals, an output enable and a clock out.

The synchronous FIFO mode uses the parallel FIFO interface signals detailed in

and an

additional two signals detailed in

This mode is not available on the 32 pin packages.

64 Pin

Package

Available

pins

11, 15,

19, 24,

28, 39,

43, 47,

51, 57,

61

12, 16,

20, 25,

29, 40,

44, 48,

52, 58,

62

48 Pin

Package

Available

pins

32 Pin

Package

Available

pins

Name

Type

Description

11, 15,

20, 31,

35, 41,

45

11, 23

29

fifo_oe#

I/O

FIFO Output enable

12,16,

21, 32,

36, 42,

46

12, 24,

30

fifo_clkout

I/O

FIFO Clock out

Table 29 Synchronous FIFO control signals

6.7.1 Read / Write Transaction Synchronous FIFO Mode

When in Synchronous FIFO interface mode, the timing of read and write operations on the FIFO interface

are shown in

and

In synchronous mode data can be transmitted to and from the FIFO module on each clock edge. An

external device synchronises to the CLKOUT output and it also has access to the output enable OE# input

to control data flow. An external device should drive output enable OE# low before pulling RD# line

down.

When bursts of data are to be read from the module RD# should be kept low. RXF# remains low when

there is still data to be read. Similarly when bursts of data are to be written to the module WR# should

be kept low. TXE# remains low when there is still space available for the data to be written.

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