Document No.: FT_000138
VINCULUM-II EMBEDDED DUAL USB HOST CONTROLLER IC Datasheet
Version -
1.2
Clearance No.: FTDI#
143
6.2.1 SPI Clock Phase Modes
SPI interface has 4 unique modes of clock phase (CPHA) and clock polarity (CPOL), known
as Mode 0, Mode 1, Mode 2 and Mode 3.
summarizes these modes and available interface and
is the function timing diagram.
For CPOL = 0, the base (inactive) level of SCLK is 0.
In this mode:
• When CPHA = 0, data is clocked in on the rising edge of SCLK, and data is clocked out on
the falling edge of SCLK.
• When CPHA = 1, data is clocked in on the falling edge of SCLK, and data is clocked out on
the rising edge of SCLK
For CPOL =1, the base (inactive) level of SCLK is 1.
In this mode:
• When CPHA = 0, data v in on the falling edge of SCLK, and data is clocked out on the
rising edge of SCLK
• When CPHA =1, data is clocked in on the rising edge of SCLK, and data is clocked out on
the falling edge of SCLK.
Mode
0
1
2
3
CPOL
0
0
1
1
CPHA
0
1
0
1
Full
Duplex
N
Y
N
Y
Half
Duplex
4 pin
N
Y
N
Y
Half
Duplex
3 pin
N
Y
N
Y
Unmanged
Y
Y
Y
Y
VNC1L
Legacy
N
N
N
N
Table 16 - Clock Phase/Polarity Modes
Figure 6-3 - SPI CPOL CPHA Function
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