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VNC2-48Q1B-TRAY 参数 Datasheet PDF下载

VNC2-48Q1B-TRAY图片预览
型号: VNC2-48Q1B-TRAY
PDF下载: 下载PDF文件 查看货源
内容描述: [Vinculum-II Embedded Dual USB Host Controller IC]
分类和应用:
文件页数/大小: 88 页 / 2234 K
品牌: FTDI [ FUTURE TECHNOLOGY DEVICES INTERNATIONAL LTD. ]
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Datasheet  
Vinculum-II Embedded Dual USB Host Controller IC  
Version 1.7  
Document No.: FT_000138 Clearance No.: FTDI#143  
Mode  
Pins  
Word Size  
Handshaking  
Speed  
Comments  
Read 66%  
Write 66%  
Read 50%  
Write 100%  
Read 100%  
Write 100%  
Read 50%  
Write 50%  
Read 100%  
Write 100%  
VNC1L  
4
4
4
3
4
12  
8
Yes  
Yes  
Yes  
Yes  
No  
Legacy mode  
Full Duplex  
MOSI becomes  
bi-directional  
MOSI becomes  
bi-directional  
Half Duplex 4 pin  
Half Duplex 3 pin  
Unmanaged  
8
8
8
Table 6.3 - SPI Slave Speeds  
VNC2 SPI Master is described in Section 6.4.1 SPI Master Signal Descriptions.  
Table 6.5 shows the SPI master signals and the available pins that they can be mapped to depending on  
the package size. Further details on the configuration of input and output signals are available in Section  
5 - I/O Multiplexer.  
6.2.1 SPI Clock Phase Modes  
SPI interface has 4 unique modes of clock phase (CPHA) and clock polarity (CPOL), known  
as Mode 0, Mode 1, Mode 2 and Mode 3. Table 6.4 summarizes these modes and available interface and  
Figure 6.3 is the function timing diagram.  
For CPOL = 0, the base (inactive) level of SCLK is 0.  
In this mode:  
When CPHA = 0, data is clocked in on the rising edge of SCLK, and data is clocked out on the  
falling edge of SCLK.  
When CPHA = 1, data is clocked in on the falling edge of SCLK, and data is clocked out on the  
rising edge of SCLK  
For CPOL =1, the base (inactive) level of SCLK is 1.  
In this mode:  
When CPHA = 0, data v in on the falling edge of SCLK, and data is clocked out on the rising edge  
of SCLK  
When CPHA =1, data is clocked in on the rising edge of SCLK, and data is clocked out on the  
falling edge of SCLK.  
Half  
Duplex  
4 pin  
Half  
Duplex  
3 pin  
Full  
Duplex  
VNC1L  
Legacy  
Mode  
CPOL  
CPHA  
Unmanaged  
0
1
2
3
0
0
1
1
0
1
0
1
N
Y
N
Y
N
Y
Y
Y
Y
Y
N
N
N
N
N
Y
N
Y
N
Y
Table 6.4 - Clock Phase/Polarity Modes  
40  
Copyright © Future Technology Devices International Limited  
 
 
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