Document Reference No.: FT_000237
V2DIP2-48 VNC2-48 Development Module Datasheet Version 1.01
Clearance No.: FTDI# 152
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3.4 Default Interface I/O Pin Configuration
The VNC2-48Q device is pre-programmed with default settings for the I/O pins however they can be
easily changed to suit a designers needs. The default interface I/O pin configuration of the VNC2-48Q
device are shown in Table 3.3
Data and Control Bus Configuration
Pin
No.
Options
Pin
Name
Ty
pe
Nam
e on
PCB
UART
Interface
SPI Slave
Interface
SPI
Master
Interface
Parallel
FIFO
Interface
Debugger
Interface
J2-8
I/O
NA
IOBUS0
IOBUS4
IOBUS5
IOBUS6
IO0
IO4
IO5
IO6
NA
NA
NA
NA
NA
NA
NA
Debug. if
NA
J2-4
J1-4
J1-5
J1-6
J1-7
J1-8
I/O
I/O
I/O
I/O
I/O
I/O
NA
NA
NA
spi_s0_clk
spi_s0_mosi
spi_s0_miso
NA
NA
NA
NA
NA
IOBUS7
IOBUS8
IO7
IO8
NA
NA
NA
spi_s0_ss#
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
spi_m_clk
spi_m_mosi
spi_m_miso
spi_m_ss#
IOBUS9
IO9
NA
J1-10
J1-11
J1-14
IOBUS10
IOBUS11
IOBUS12
IOBUS13
IOBUS14
IOBUS15
IOBUS16
IOBUS17
IOBUS18
IOBUS19
IOBUS20
IO10
IO11
IO12
IO13
IO14
IO15
IO16
IO17
IO18
IO19
IO20
I/O
I/O
I/O
NA
NA
NA
NA
uart_txd
NA
NA
NA
NA
NA
NA
NA
NA
J1-16
J1-17
J1-18
J1-19
J1-20
J2-20
J2-19
J2-18
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
uart_rxd
uart_rts#
uart_cts#
uart_dtr#
uart_dsr#
uart_dcd#
uart_ri#
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
uart_tx_active
NA
Table 3.3 - Default Interface I/O Pin Configuration
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9
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