Document Reference No.: FT_000247
V2-EVAL Vinculum II Evaluation Board Datasheet Version 2.0
Clearance No.: FTDI#148
5.17
VNC2 Daughterboard Connector – J1
1
16
Figure 5.22
VNC2 Daughterboard Connector J1
VCN2 Pin No
Schematic
Connector
IO
Description
Signal Name(43)
Pin
type
32-PIN 48-PIN 64-PIN
3.3V
3.3V
GND
1
2
3
-
-
-
-
-
-
-
-
-
-
-
-
3.3V power rail.
3.3V power rail.
Ground pin.
USB1 transceiver, data line positive connected
to CN1.
USB1 transceiver, data line minus connected to
CN1.
USB1DP
USB1DM
4
5
17
18
25
26
33
34
IO
IO
SPI_S0_CLK
SPI_S0_MOSI
SPI_S0_MISO
SPI_S0_CS#
6
7
8
9
29
30
31
32
15
16
18
19
51
52
55
56
IO
IO
IO
IO
Connected to P1 pin 38 / CN7 pin 1.
Connected to P1 pin 39 / CN7 pin 2.
Connected to P1 pin 40 / CN7 pin 3.
Connected to P1 pin 40 / CN7 pin 4.
USB2 transceiver, data line positive connected
to CN2.
USB2 transceiver, data line minus connected to
CN2.
Connected to
P1 pin 25 / CN10 pin 1 / CN5 pin 5.
Connected to
P1 pin 26 / CN10 pin 2 / CN5 pin 6.
Connected to
P1 pin 27 / CN10 pin 3 / CN5 pin 7.
Connected to
USB2DP
USB2DM
V_TXD
10
11
12
13
14
15
16
20
21
23
24
25
26
-
28
29
31
32
33
34
35
36
37
39
40
41
42
43
IO
IO
IO
IO
IO
IO
IO
V_RXD
V_RTS#
V_CTS#
P1 pin 28 / CN10 pin 4 / CN5 pin 8.
Connected to
P1 pin 29 / CN10 pin 5 / CN6 pin 1.
V_DTR#
Notes:
(43) The signal names relate to the labels used on pages 1 & 2 of the V2-EVAL base board schematic. Unless
otherwise stated, the function of the IO signals is be set by the user application running on the VNC2.
Table 5.18 Connector J1 Pinout
Copyright © 2010 Future Technology Devices International Limited
34
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