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IOBUS4 参数 Datasheet PDF下载

IOBUS4图片预览
型号: IOBUS4
PDF下载: 下载PDF文件 查看货源
内容描述: [Vinculum-II Embedded Dual USB Host Controller IC]
分类和应用:
文件页数/大小: 88 页 / 2234 K
品牌: FTDI [ FUTURE TECHNOLOGY DEVICES INTERNATIONAL LTD. ]
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Datasheet  
Vinculum-II Embedded Dual USB Host Controller IC  
Version 1.7  
Document No.: FT_000138 Clearance No.: FTDI#143  
3.12 Pin Configuration Input / Output  
VNC2 has multiple interfaces available for connecting to external devices. These are UART, FIFO, SPI  
slave, SPI master, GPIO and PWM. The Interface I/O Multiplexer is used to share the available I/O Pins  
between each peripheral.  
VNC2 is configured with default settings for the I/O pins however they can be easily changed to suit the  
needs of a designer. This is explained in Section 5 I/O Multiplexer. Default configuration for each  
package type is shown in Table 3.4- Default I/O Configuration. The signal names are also indicated  
for the VNC1L device as it is pin-compatible with the 48 pin LQFP VNC2 device.  
Note: The default values of the pins listed in the following table are only available when the  
I/O Mux is enabled. A blank VNC2 chip defaults to all I/O pins as inputs.  
Pin No  
Name  
64 Pin  
48 Pin  
32 PIN  
Default  
Type Description  
(VINC1-L)  
Default  
Default  
64  
Pin  
48  
Pin  
32  
Pin  
IOBUS0  
(BDBUS0)  
11  
11  
11  
debug_if  
debug_if  
debug_if  
I/O  
GPIO  
IOBUS1  
(BDBUS1)  
12  
13  
14  
15  
16  
17  
18  
19  
20  
22  
23  
24  
25  
26  
12  
13  
14  
15  
16  
18  
19  
20  
21  
22  
23  
31  
32  
33  
12  
14  
15  
23  
24  
25  
26  
29  
30  
31  
32  
-
Input  
pwm[1]  
pwm[2]  
gpio[A1]  
gpio[A2]  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
GPIO  
GPIO  
GPIO  
GPIO  
GPIO  
GPIO  
GPIO  
GPIO  
GPIO  
GPIO  
GPIO  
GPIO  
GPIO  
GPIO  
IOBUS2  
(BDBUS2)  
Input  
IOBUS3  
(BDBUS3)  
Input  
pwm[3]  
gpio[A3]  
IOBUS4  
(BDBUS4)  
fifo_data[0]  
fifo_data[1]  
fifo_data[2]  
fifo_data[3]  
fifo_data[4]  
fifo_data[5]  
fifo_data[6]  
fifo_data[7]  
fifo_rxf#  
spi_s0_clk  
spi_s0_mosi  
spi_s0_miso  
spi_s0_ss#  
spi_m_clk  
spi_m_mosi  
spi_m_miso  
spi_m_ss_0#  
uart_txd  
uart_txd  
IOBUS5  
(BDBUS5)  
uart_rxd  
IOBUS6  
(BDBUS6)  
uart_rts#  
uart_cts#  
spi_s0_clk  
spi_s0_mosi  
spi_s0_miso  
spi_s0_ss#  
IOBUS7  
(BDBUS7)  
IOBUS8  
(BCBUS0)  
IOBUS9  
(BCBUS1)  
IOBUS10  
(BCBUS2)  
IOBUS11  
(BCBUS3)  
IOBUS12  
(ADBUS0)  
IOBUS13  
(ADBUS1)  
-
fifo_txe#  
fifo_rd#  
uart_rxd  
IOBUS14  
(ADBUS2)  
-
uart_rts#  
18  
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