欢迎访问ic37.com |
会员登录 免费注册
发布采购

FT51BQ-R 参数 Datasheet PDF下载

FT51BQ-R图片预览
型号: FT51BQ-R
PDF下载: 下载PDF文件 查看货源
内容描述: [Advanced Microcontroller with 8051 Compatible Core]
分类和应用: 微控制器
文件页数/大小: 43 页 / 1683 K
品牌: FTDI [ FUTURE TECHNOLOGY DEVICES INTERNATIONAL LTD. ]
 浏览型号FT51BQ-R的Datasheet PDF文件第35页浏览型号FT51BQ-R的Datasheet PDF文件第36页浏览型号FT51BQ-R的Datasheet PDF文件第37页浏览型号FT51BQ-R的Datasheet PDF文件第38页浏览型号FT51BQ-R的Datasheet PDF文件第39页浏览型号FT51BQ-R的Datasheet PDF文件第40页浏览型号FT51BQ-R的Datasheet PDF文件第42页浏览型号FT51BQ-R的Datasheet PDF文件第43页  
FT51A Advanced MCU with 8051 Compatible Core IC Datasheet  
Version 1.5  
Document No.: FT_000877  
Clearance No.: FTDI#420  
Register  
Address  
(0xB8)  
(0xB9)  
Register Name  
Description  
DMA_IO_ADDR_L_1  
DMA_IO_ADDR_U_1  
DMA IO Addr Register (Lower Bits)  
IO DMA IO Addr Register (Upper Bits)  
IO DMA Transfer Byte Count Register  
(Lower Bits)  
IO DMA Transfer Byte Count Register  
(Upper Bits)  
IO DMA Current Byte Count Register  
(Lower Bits)  
IO DMA Current Byte Count Register  
(Upper Bits)  
(0xBA)  
(0xBB)  
(0xBC)  
(0xBD)  
DMA_TRANS_CNT_L_1  
DMA_TRANS_CNT_U_1  
DMA_CURR_CNT_L_1  
DMA_CURR_CNT_U_1  
(0xBE)  
(0xBF)  
(0xC0)  
(0xC1)  
DMA_FIFO_DATA_1  
DMA_AFULL_TRIGGER_1  
DMA_CONTROL_2  
DMA_ENABLE_2  
IO DMA FIFO DATA  
IO DMA Almost Full Flag Trigger Value  
DMA Control Register  
IO DMA Enable Register  
DMA IO Interrupt Enable & Control  
Register  
DMA IO Interrupt Register  
DMA IO Source Mem Addr Register  
(Lower Bits)  
(0xC2)  
(0xC3)  
(0xC4)  
DMA_IRQ_ENA_2  
DMA_IRQ_2  
DMA_SRC_MEM_ADDR_L_2  
DMA IO Source Mem Addr Register  
(Upper Bits)  
DMA IO Destination Mem Addr Register  
(Lower Bits)  
DMA IO Destination Mem Addr Register  
(Upper Bits)  
(0xC5)  
(0xC6)  
(0xC7)  
DMA_SRC_MEM_ADDR_U_2  
DMA_DEST_MEM_ADDR_L_2  
DMA_DEST_MEM_ADDR_U_2  
(0xC8)  
(0xC9)  
DMA_IO_ADDR_L_2  
DMA_IO_ADDR_U_2  
DMA IO Addr Register (Lower Bits)  
IO DMA IO Addr Register (Upper Bits)  
IO DMA Transfer Byte Count Register  
(Lower Bits)  
IO DMA Transfer Byte Count Register  
(Upper Bits)  
IO DMA Current Byte Count Register  
(Lower Bits)  
IO DMA Current Byte Count Register  
(Upper Bits)  
(0xCA)  
(0xCB)  
(0xCC)  
(0xCD)  
DMA_TRANS_CNT_L_2  
DMA_TRANS_CNT_U_2  
DMA_CURR_CNT_L_2  
DMA_CURR_CNT_U_2  
(0xCE)  
(0xCF)  
(0xD0)  
(0xD1)  
DMA_FIFO_DATA_2  
DMA_AFULL_TRIGGER_2  
DMA_CONTROL_3  
DMA_ENABLE_3  
IO DMA FIFO DATA  
IO DMA Almost Full Flag Trigger Value  
DMA Control Register  
IO DMA Enable Register  
DMA IO Interrupt Enable & Control  
Register  
DMA IO Interrupt Register  
DMA IO Source Mem Addr Register  
(Lower Bits)  
(0xD2)  
(0xD3)  
(0xD4)  
DMA_IRQ_ENA_3  
DMA_IRQ_3  
DMA_SRC_MEM_ADDR_L_3  
DMA IO Source Mem Addr Register  
(Upper Bits)  
DMA IO Destination Mem Addr Register  
(Lower Bits)  
DMA IO Destination Mem Addr Register  
(Upper Bits)  
(0xD5)  
(0xD6)  
(0xD7)  
DMA_SRC_MEM_ADDR_U_3  
DMA_DEST_MEM_ADDR_L_3  
DMA_DEST_MEM_ADDR_U_3  
(0xD8)  
(0xD9)  
DMA_IO_ADDR_L_3  
DMA_IO_ADDR_U_3  
DMA IO Addr Register (Lower Bits)  
IO DMA IO Addr Register (Upper Bits)  
IO DMA Transfer Byte Count Register  
(Lower Bits)  
IO DMA Transfer Byte Count Register  
(Upper Bits)  
(0xDA)  
(0xDB)  
(0xDC)  
DMA_TRANS_CNT_L_3  
DMA_TRANS_CNT_U_3  
DMA_CURR_CNT_L_3  
IO DMA Current Byte Count Register  
(Lower Bits)  
Copyright © Future Technology Devices International Limited  
41  
 复制成功!