FT4232H QUAD HIGH SPEED USB TO MULTIPURPOSE UART/MPSSE IC
Datasheet
Version 2.4
Document No.: FT_000060 Clearance No.: FTDI#78
3.1.2
Pin Descriptions
This section describes the operation of the FT4232H pins for 64-pin LQFP and 64-pin QFN. Both the 64-pin
QFN and LQFP packages have the same function on each pin. The function of many pins is determined by
the configuration of the FT4232H. The following table details the function of each pin dependent on the
configuration of the interface. Each of the functions are described in Table 3.1.
(Note: The convention used throughout this document for active low signals is the signal name followed by
#)
FT4232HL and FT4232HQ (64-pin)
Pins
Pin Name
Pin functions (depend on configuration)
ASYNC Serial
(RS232)
ASYNC Bit-
bang
SYNC Bit-
bang
Pin #
MPSSE
Channel A
16
17
18
19
21
22
23
24
ADBUS0
ADBUS1
ADBUS2
ADBUS3
ADBUS4
ADBUS5
ADBUS6
ADBUS7
TXD
RXD
RTS#
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
TCK/SK
TDI/DO
TDO/DI
TMS/CS
GPIOL0
GPIOL1
GPIOL2
GPIOL3
CTS#
DTR#
DSR#
DCD#
RI#/ TXDEN*
Channel B
26
27
28
29
30
32
33
34
BDBUS0
BDBUS1
BDBUS2
BDBUS3
BDBUS4
BDBUS5
BDBUS6
BDBUS7
TXD
RXD
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
TCK/SK
TDI/DO
TDO/DI
TMS/CS
GPIOL0
GPIOL1
GPIOL2
GPIOL3
RTS#
CTS#
DTR#
DSR#
DCD#
RI#/ TXDEN*
Channel C
38
39
40
41
43
44
45
46
CDBUS0
CDBUS1
CDBUS2
CDBUS3
CDBUS4
CDBUS5
CDBUS6
CDBUS7
TXD
RXD
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
RS232 or Bit-Bang interface
RS232 or Bit-Bang interface
RS232 or Bit-Bang interface
RS232 or Bit-Bang interface
RS232 or Bit-Bang interface
RS232 or Bit-Bang interface
RS232 or Bit-Bang interface
RS232 or Bit-Bang interface
RTS#
CTS#
DTR#
DSR#
DCD#
RI#/ TXDEN*
Channel D
48
52
53
54
55
57
58
59
60
36
DDBUS0
DDBUS1
DDBUS2
DDBUS3
DDBUS4
DDBUS5
DDBUS6
DDBUS7
PWREN#
SUSPEND#
TXD
RXD
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
RS232 or Bit-Bang interface
RS232 or Bit-Bang interface
RS232 or Bit-Bang interface
RS232 or Bit-Bang interface
RS232 or Bit-Bang interface
RS232 or Bit-Bang interface
RS232 or Bit-Bang interface
RS232 or Bit-Bang interface
PWREN#
RTS#
CTS#
D2
D3
DTR#
D4
DSR#
D5
DCD#
D6
RI#/ TXDEN*
PWREN#
SUSPEND#
D7
PWREN#
PWREN#
SUSPEND#
SUSPEND#
SUSPEND#
Configuration memory interface
63
62
61
EECS
EECLK
EEDATA
Table 3.1 FT4232H Pin Configurations for 64-pin QFN and LQFP package
* RI#/ or TXDEN is selectable in the EEPROM. Default is RI#.
Copyright © Future Technology Devices International Limited
8
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