FT4232H QUAD HIGH SPEED USB TO MULTIPURPOSE UART/MPSSE IC
Datasheet
Version 2.4
Document No.: FT_000060 Clearance No.: FTDI#78
4 Function Description
The FT4232H is FTDI’s 5th generation of USB devices. The FT4232H is a USB 2.0 High Speed (480Mb/s) to
UART/MPSSE ICs. It has the capability of being configured in a variety of industry standard serial
interfaces.
The FT4232H has four independent configurable interfaces. Two of these interfaces can be configured as
UART, JTAG, SPI, I2C or bit-bang mode, using an MPSSE, with independent baud rate generators. The
remaining two interfaces can be configured as UART or bit-bang.
4.1 Key Features
USB High Speed to Quad Interface. The FT4232H is a USB 2.0 High Speed (480Mbits/s) to four
independent flexible/configurable serial interfaces.
Functional Integration. The FT4232H integrates a USB protocol engine which controls the physical
Universal Transceiver Macrocell Interface (UTMI) and handles all aspects of the USB 2.0 High Speed
interface. The FT4232H includes an integrated +1.8V Low Drop-Out (LDO) regulator and 12MHz to 480MHz
PLL. It also includes 2kbytes Tx and Rx data buffers per channel. The FT4232H effectively integrates the
entire USB protocol on a chip.
MPSSE. Multi-Purpose Synchronous Serial Engines (MPSSE), capable of speeds up to 30 Mbits/s, provides
flexible synchronous interface configurations.
Data Transfer rate. The FT4232H supports a data transfer rate up to 12 Mbit/s when configured as an
RS232/RS422/RS485 UART interface. Please note the FT4232H does not support the baud rates of 7
Mbaud 9 Mbaud, 10 Mbaud and 11 Mbaud.
Latency Timer. This is really a feature of the driver and is used to as a timeout to flush short packets of
data back to the PC. The default is 16ms, but it can be altered between 0ms and 256ms. At 0ms latency
you get a packet transfer on every high speed micro frame.
4.2 Functional Block Descriptions
Quad Multi-Purpose UART/MPSSE Controllers. The FT4232H has four independent UART/MPSSE
Controllers. These blocks control the UART data or control the Bit-Bang mode if selected by the SETUP
command. The blocks used on channel A and channel B also contain a MPSSE (Multi-Protocol Synchronous
Serial Engine) in each of them which can be used independently of each other and the remaining UART
channels. Using this it can be configured under software command to have 1 MPSSE + 3 UARTS (each
UART can be set to Bit Bang mode to gain extra I/O if required) or 2 MPSSE + 2 UARTS.
USB Protocol Engine and FIFO control. The USB Protocol Engine controls and manages the interface
between the UTMI PHY and the FIFOs of the chip. It also handles power management and the USB protocol
specification.
Dual Port FIFO TX Buffer (2Kbytes per channel). Data from the Host PC is stored in these buffers to
be used by the Multi-purpose UART/FIFO controllers. This is controlled by the USB Protocol Engine and
FIFO control block.
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