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FT4232H-56Q 参数 Datasheet PDF下载

FT4232H-56Q图片预览
型号: FT4232H-56Q
PDF下载: 下载PDF文件 查看货源
内容描述: [Quad High Speed USB to Multipurpose UART/MPSSE IC]
分类和应用:
文件页数/大小: 55 页 / 1663 K
品牌: FTDI [ FUTURE TECHNOLOGY DEVICES INTERNATIONAL LTD. ]
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FT4232H QUAD HIGH SPEED USB TO MULTIPURPOSE UART/MPSSE IC  
Datasheet  
Version 2.4  
Document No.: FT_000060 Clearance No.: FTDI#78  
3.1.4.3  
FT4232H pins used in an MPSSE  
The FT4232H channel A and channel B, each have a Multi-Protocol Synchronous Serial Engine (MPSSE).  
Each MPSSE can be independently configured to a number of industry standard serial interface protocols  
such as JTAG, I2C or SPI, or it can be used to implement a proprietary bus protocol. For example, it is  
possible to use one of the FT4232H’s channels (e.g. channel A) to connect to an SRAM configurable FPGA  
such as supplied by Altera or Xilinx. The FPGA device would normally be un-configured (i.e. have no  
defined function) at power-up. Application software on the PC could use the MPSSE to download  
configuration data to the FPGA over USB. This data would define the hardware function on power up. The  
other MPSSE channel (e.g. channel B) would be available for another serial interface function while channel  
C and channel D can be configured as UART or bit-bang mode. Alternatively each MPSSE can be used to  
control a number of GPIO pins. When configured in this mode, the pins used and the descriptions of the  
signals are shown in Table 3.7  
Channel A  
Pin No.  
Channel B  
Pin No.  
Name  
Type  
MPSSE Configuration Description  
Clock Signal Output. For example:  
JTAG TCK, Test interface clock  
SPI SK, Serial Clock  
TCK/SK  
OUTPUT  
16  
17  
26  
27  
Serial Data Output. For example:  
JTAG TDI, Test Data Input  
SPI DO, serial data output  
TDI/DO  
TDO/DI  
TMS/CS  
OUTPUT  
INPUT  
Serial Data Input. For example:  
JTAG TDO, Test Data output  
SPI DI, Serial Data Input  
18  
19  
28  
29  
Output Signal Select. For example:  
JTAG TMS, Test Mode Select  
SPI CS, Serial Chip Select  
OUTPUT  
GPIOL0  
GPIOL1  
GPIOL2  
GPIOL3  
I/O  
I/O  
I/O  
I/O  
General Purpose input/output  
General Purpose input/output  
General Purpose input/output  
General Purpose input/output  
21  
22  
23  
24  
30  
32  
33  
34  
Table 3.7 Channel A and Channel B MPSSE Configured Pin Descriptions  
For a functional description of this mode, please refer to section 4.4.  
When either Channel A or Channel B or both channels are used in MPSSE mode, Channel C and Channel D  
can be configured as asynchronous serial interface (RS232/422/485) or Bit-Bang mode or a combination of  
both.  
Copyright © Future Technology Devices International Limited  
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