FT232BL USB UART ( USB - Serial) I.C.
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x8 Clock Multiplier
The x8 Clock Multiplier takes the 6MHz input
from the Oscillator cell and generates a 12MHz
reference clock for the SIE, USB Protocol Engine
and UART FIFO controller blocks. It also generates
a 48MHz reference clock for the USB DPPL and
the Baud Rate Generator blocks.
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Serial Interface Engine (SIE)
The Serial Interface Engine (SIE) block performs
the Parallel to Serial and Serial to Parallel
conversion of the USB data. In accordance to the
USB 2.0 specification, it performs bit stuffing / un-
stuffing and CRC5 / CRC16 generation / checking
on the USB data stream.
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USB Protocol Engine
The USB Protocol Engine manages the data
stream from the device USB control endpoint. It
handles the low level USB protocol (Chapter 9)
requests generated by the USB host controller
and the commands for controlling the functional
parameters of the UART.
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Dual Port TX Buffer (128 bytes)
Data from the USB data out endpoint is stored
in the Dual Port TX buffer and removed from the
buffer to the UART transmit register under control
of the UART FIFO controller.
Dual Port RX Buffer (384 bytes)
Data from the UART receive register is stored in
the Dual Port RX buffer prior to being removed by
the SIE on a USB request for data from the device
data in endpoint.
UART FIFO Controller
The UART FIFO controller handles the transfer of
data between the Dual Port RX and TX buffers and
the UART transmit and receive registers.
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UART
The UART performs asynchronous 7 / 8 bit
Parallel to Serial and Serial to Parallel conversion
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of the data on the RS232 (RS422 and RS485)
interface. Control signals supported by the UART
include RTS, CTS, DSR , DTR, DCD and RI.
The UART provides a transmitter enable control
signal (TXDEN) to assist with interfacing to
RS485 transceivers. The UART supports RTS/
CTS, DSR/DTR and X-On/X-Off handshaking
options. Handshaking, where required, is handled
in hardware to ensure fast response times. The
UART also supports the RS232 BREAK setting
and detection conditions.
Baud Rate Generator
The Baud Rate Generator provides a x16 clock
input to the UART from the 48MHz reference clock
and consists of a 14 bit prescaler and 3 register
bits which provide fine tuning of the baud rate
(used to divide by a number plus a fraction). This
determines the Baud Rate of the UART which is
programmable from 183 baud to 3 million baud.
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RESET Generator
The Reset Generator Cell provides a reliable
power-on reset to the device internal circuitry
on power up. An additional RESET# input and
RSTOUT# output are provided to allow other
devices to reset the FT232BL or the FT232BL
to reset other devices respectively. During reset,
RSTOUT# is driven low, otherwise it drives out
at the 3.3V provided by the onboard regulator.
RSTOUT# can be used to control the 1.5k
pull-up on USBDP directly where delayed USB
enumeration is required. It can also be used to
reset other devices. RSTOUT# will stay high-
impedance for approximately 5ms after VCC
has risen above 3.5V AND the device oscillator is
running AND RESET# is high. RESET# should
be tied to VCC unless it is a requirement to reset
the device from external logic or an external reset
generator i.c.
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DS232BL Version 1.8
© Future Technology Devices Intl. Ltd. 2005
Page 6 of 25
FTDI [ FUTURE TECHNOLOGY DEVICES INTERNATIONAL LTD. ]
