FT232BL USB UART ( USB - Serial) I.C.
2.0
Enhancements
This section summarises the enhancements of the 2
nd
generation device compared to its FT8U232AM predecessor.
For further details, consult the device pin-out description and functional descriptions.
•
Integrated Power-On-Reset (POR) Circuit
The device now incorporates an internal POR
function. The existing RESET# pin is maintained
in order to allow external logic to reset the device
where required, however for many applications
this pin can now simply be hard wired to VCC. In
addition, a new reset output pin (RSTOUT#) is
provided in order to allow the new POR circuit to
provide a stable reset to external MCU and other
devices. RSTOUT# was the TEST pin on the
previous generation of devices.
•
Integrated RCCLK Circuit
In the previous devices, an external RC circuit
was required to ensure that the oscillator and
clock multiplier PLL frequency was stable prior
to enabling the clock internal to the device. This
circuit is now embedded on-chip – the pin assigned
to this function is now designated as the TEST pin
and should be tied to GND for normal operation.
•
Integrated Level Converter on UART interface
and control signals
The previous devices would drive the UART and
control signals at 5V CMOS logic levels. The
new device has a separate VCC-IO pin allowing
the device to directly interface to 3.3V and other
logic families without the need for external level
converter I.C.’s
•
Improved Power Management control for USB
Bus Powered, high current devices
The previous devices had a USBEN pin, which
became active when the device was enumerated
by USB. To provide power control, this signal had
to be externally gated with SLEEP# and RESET#.
•
•
Lower Suspend Current
Integration of RCCLK within the device and internal
design improvements reduce the suspend current
of the FT232BL to under 200uA (excluding the 1.5k
pull-up on USBDP) in USB suspend mode. This
allows greater margin for peripherals to meet the
USB Suspend current limit of 500uA.
Support for USB Isochronous Transfers
Whilst USB Bulk transfer is usually the best
choice for data transfer, the scheduling time of the
data is not guaranteed. For applications where
scheduling latency takes priority over data integrity
such as transferring audio and low bandwidth
video data, the new device now offers an option of
USB Isochronous transfer via an option bit in the
EEPROM.
This gating is now done on-chip - USBEN has
now been replaced with the new PWREN# signal
which can be used to directly drive a transistor or
P-Channel MOSFET in applications where power
switching of external circuitry is required. A new
EEPROM based option makes the device pull
gently down its UART interface lines when the
power is shut off (PWREN# is High). In this mode,
any residual voltage on external circuitry is bled to
GND when power is removed thus ensuring that
external circuitry controlled by PWREN# resets
reliably when power is restored.
DS232BL Version 1.8
© Future Technology Devices Intl. Ltd. 2005
Page 2 of 25
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