FT2232HQ-4000 参数 Datasheet PDF下载

Document No.: FT_000061

FT2232H DUAL HIGH SPEED USB TO MULTIPURPOSE UART/FIFO IC

Datasheet Version 2.09

Clearance No.: FTDI#77

4.7.1 MCU Host Bus Emulation Mode Signal Timing – Write Cycle

Figure 4.10 MCU Host Bus Emulation Mode Signal Waveforms – write cycle

Table 4.4 MCU Host Bus Emulation Mode Signal Timings – write cycle

When Div By 5 is on the device will return 2 bytes when doing a read. When it is off the device will return 1

byte when doing a read. The clock period is 16.67 nS so most devices would need the Div By 5 to be set on.

IORDY can be held low permanently to extend all cycles.

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