Overview
Security
Engine
DDR/DDR2/
Memory Controller
DDR
SDRAM
512-Kbyte
L2 Cache/
SRAM
Flash
SDRAM
GPIO
XOR
Engine
Local Bus Controller
e500 Core
Programmable Interrupt
Controller (PIC)
IRQs
e500
Coherency
Module
32-KbyteL1
32-Kbyte
L1 Data
Cache
Core Complex
Bus
Instruction
Cache
Serial
DUART
2
I C
2
I C
Controller
Serial RapidIO™
2
I C
2
or
4x RapidIO
x8 PCI Express
I C
Controller
PCI Express
MII, GMII, TBI,
RTBI, RGMII,
RMII
eTSEC
10/100/1Gb
eTSEC
OceaN
Switch
Fabric
PCI 32-bit
66 MHz
32-bit PCI Bus Interface
(If 64-bit not used)
MII, GMII, TBI,
RTBI, RGMII,
RMII
10/100/1Gb
eTSEC
32-bit PCI/
64-bit PCI/PCI-X
Bus Interface
PCI/PCI-X
133 MHz
MII, GMII, TBI,
RTBI, RGMII,
RMII
10/100/1Gb
eTSEC
4-Channel DMA
Controller
RTBI, RGMII,
RMII
10/100/1Gb
Figure 1. MPC8548E Block Diagram
1.1
Key Features
The following list provides an overview of the MPC8548E feature set:
High-performance 32-bit core built on Power Architecture™ technology.
•
— 32-Kbyte L1 instruction cache and 32-Kbyte L1 data cache with parity protection. Caches can
be locked entirely or on a per-line basis, with separate locking for instructions and data.
— Signal-processing engine (SPE) APU (auxiliary processing unit). Provides an extensive
instruction set for vector (64-bit) integer and fractional operations. These instructions use both
the upper and lower words of the 64-bit GPRs as they are defined by the SPE APU.
— Double-precision floating-point APU. Provides an instruction set for double-precision (64-bit)
floating-point instructions that use the 64-bit GPRs.
— 36-bit real addressing
— Embedded vector and scalar single-precision floating-point APUs. Provide an instruction set
for single-precision (32-bit) floating-point instructions.
— Memory management unit (MMU). Especially designed for embedded applications. Supports
4-Kbyte–4-Gbyte page sizes.
— Enhanced hardware and software debug support
MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 6
2
Freescale Semiconductor
FREESCALE [ Freescale ]
