Clocking
15.2 Platform/System PLL Ratio
The platform clock is the clock that drives the L2 cache, the DDR SDRAM data rate, and the e500 core
complex bus (CCB), and is also called the CCB clock. The values are determined by the binary value on
LA[28:31] at power up, as shown in
There is no default for this PLL ratio; these signals must be pulled to the desired values.
Table 56. CCB Clock Ratio
Binary Value of
LA[28:31] Signals
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Ratio Description
16:1 ratio CCB clock: SYSCLK (PCI bus)
Reserved
2:1 ratio CCB clock: SYSCLK (PCI bus)
3:1 ratio CCB clock: SYSCLK (PCI bus)
4:1 ratio CCB clock: SYSCLK (PCI bus)
5:1 ratio CCB clock: SYSCLK (PCI bus)
6:1 ratio CCB clock: SYSCLK (PCI bus)
Reserved
8:1 ratio CCB clock: SYSCLK (PCI bus)
9:1 ratio CCB clock: SYSCLK (PCI bus)
10:1 ratio CCB clock: SYSCLK (PCI bus)
Reserved
12:1 ratio CCB clock: SYSCLK (PCI bus)
Reserved
Reserved
Reserved
15.3 e500 Core PLL Ratio
describes the clock ratio between the e500 core complex bus (CCB) and the e500 core clock. This
ratio is determined by the binary value of LALE and LGPL2 at power up, as shown in
Table 57. e500 Core to CCB Ratio
Binary Value of
LALE, LGPL2 Signals
00
01
10
11
Ratio Description
2:1 e500 core:CCB
5:2 e500 core:CCB
3:1 e500 core:CCB
7:2 e500 core:CCB
MPC8540 Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
77
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