High-Speed Serial Interfaces (HSSI)
Figure 62 shows the SerDes reference clock connection reference circuits for a single-ended clock driver.
It assumes the DC levels of the clock driver are compatible with device SerDes reference clock input’s DC
requirement.
Single-Ended CLK
Driver Chip
MPC8378E
Total 50 Ω. Assume clock driver’s
output impedance is about 16 Ω.
50 Ω
SDn_REF_CLK
33 Ω
Clock Driver
CLK_Out
SerDes Refer.
CLK Receiver
100 Ω differential PWB trace
SDn_REF_CLK
50
Ω
50 Ω
Figure 62. Single-Ended Connection (Reference Only)
20.2.4 AC Requirements for SerDes Reference Clocks
The clock driver selected should provide a high quality reference clock with low phase noise and
cycle-to-cycle jitter. Phase noise less than 100 KHz can be tracked by the PLL and data recovery loops and
is less of a problem. Phase noise above 15 MHz is filtered by the PLL. The most problematic phase noise
occurs in the 1–15 MHz range. The source impedance of the clock driver should be 50 Ω to match the
transmission line and reduce reflections which are a source of noise to the system.
Table 66 describes some AC parameters common to SGMII and PCI Express protocols.
Table 66. SerDes Reference Clock Common AC Parameters
At recommended operating conditions with XVDD_SRDS or XVDD_SRDS = 1.0 V ± 5%.
Parameter
Symbol
Min
Max
Unit
Notes
Rising Edge Rate
Falling Edge Rate
Rise Edge Rate
Fall Edge Rate
1.0
1.0
200
—
4.0
4.0
V/ns
V/ns
mV
2, 3
2, 3
2
Differential Input High Voltage
Differential Input Low Voltage
V
—
IH
V
–200
mV
2
IL
™
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
86
FREESCALE [ Freescale ]
