SPI
Table 65. SPI AC Timing Specifications (continued)
Parameter
SPI inputs—Slave mode (external clock) input hold time
Symbol
1
t
NEIXKH
Min
2
Max
—
Unit
ns
Note:
1
The symbols used for timing specifications follow the pattern of t
(first two letters of functional block)(signal)(state) (reference)(state)
for
inputs and t
(first two letters of functional block)(reference)(state)(signal)(state)
for outputs. For example, t
NIKHOV
symbolizes the internal
timing (NI) for the time SPICLK clock reference (K) goes to the high state (H) until outputs (O) are invalid (X).
2. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings
are measured at the pin. The maximum SPICLK input frequency is 66.666 MHz.
provides the AC test load for the SPI.
Output
Z
0
= 50
Ω
R
L
= 50
Ω
OVDD/2
Figure 51. SPI AC Test Load
through
represent the AC timing from
Note that although the specifications
generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge
is the active edge.
shows the SPI timing in slave mode (external clock).
SPICLK (input)
t
NEIVKH
tN
EIXKH
Input Signals:
SPIMOSI
(See Note)
Output Signals:
SPIMISO
(See Note)
t
NEKHOV
Note:
The clock edge is selectable on SPI.
Figure 52. SPI AC Timing in Slave Mode (External Clock) Diagram
MPC8378E PowerQUICC
™
II Pro Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
77