DUART
shows the DDR1 and DDR2 SDRAM output timing diagram.
MCK[n]
MCK[n]
t
MCK
t
DDKHAS
,t
DDKHCS
t
DDKHAX
,t
DDKHCX
ADDR/CMD
Write A0
t
DDKHMP
t
DDKHMH
MDQS[n]
t
DDKHDS
t
DDKLDS
MDQ[x]
t
DDKHDX
D0
D1
t
DDKLDX
t
DDKHME
NOOP
Figure 5. DDR1 and DDR2 SDRAM Output Timing Diagram
provides the AC test load for the DDR bus.
Output
Z
0
= 50
Ω
GVDD/2
R
L
= 50
Ω
Figure 6. DDR AC Test Load
7
DUART
This section describes the DC and AC electrical specifications for the DUART interface of the
MPC8378E.
7.1
DUART DC Electrical Characteristics
Table 21. DUART DC Electrical Characteristics
Parameter
Symbol
V
IH
V
IL
Min
2
–0.3
Max
OV
DD
+ 0.3
0.8
Unit
V
V
provides the DC electrical characteristics for the DUART interface of the device.
High-level input voltage
Low-level input voltage OV
DD
MPC8378E PowerQUICC
™
II Pro Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
21
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
