General
• Bus clock = 36 MHz
• Flash clock = 24 MHz
Table 5. Power mode transition operating behaviors
Symbol
Description
Min.
Max.
Unit
Notes
tPOR
After a POR event, amount of time from the point VDD
reaches 1.71 V to execution of the first instruction
across the operating temperature range of the chip.
—
300
μs
1
—
—
—
—
—
—
112
74
μs
μs
μs
μs
μs
μs
• VLLS1 → RUN
• VLLS2 → RUN
• VLLS3 → RUN
• LLS → RUN
73
5.9
5.8
4.2
• VLPS → RUN
• STOP → RUN
1. Normal boot (FTFL_OPT[LPBOOT]=1)
5.2.5 Power consumption operating behaviors
Table 6. Power consumption operating behaviors
Symbol Description
Min.
Typ.
Max.
Unit
Notes
IDDA
Analog supply current
—
—
See note
mA
1
IDD_RUN Run mode current — all peripheral clocks
disabled, code executing from flash
2
• @ 1.8V
• @ 3.0V
—
—
21.5
21.5
25
30
mA
mA
IDD_RUN Run mode current — all peripheral clocks
enabled, code executing from flash
3, 4
• @ 1.8V
• @ 3.0V
• @ 25°C
• @ 125°C
—
31
34
mA
—
—
—
31
32
34
39
—
mA
mA
mA
IDD_WAIT Wait mode high frequency current at 3.0 V — all
peripheral clocks disabled
12.5
2
5
IDD_WAIT Wait mode reduced frequency current at 3.0 V
— all peripheral clocks disabled
—
7.2
—
mA
Table continues on the next page...
K51 Sub-Family Data Sheet, Rev. 2, 4/2012.
Freescale Semiconductor, Inc.
15
FREESCALE [ Freescale ]
