Family Configurations
n
— 2 (n ≤ 0 ≤ 15) low-power divider for extremely low frequency operation
•
Interrupt controller
— Uniquely programmable vectors for all interrupt sources
— Fully programmable level and priority for all peripheral interrupt sources
— Seven external interrupt signals with fixed level and priority
— Unique vector number for each interrupt source
— Ability to mask any individual interrupt source or all interrupt sources (global mask-all)
— Support for hardware and software interrupt acknowledge (IACK) cycles
— Combinatorial path to provide wake-up from low-power modes
DMA controller
•
— Four fully programmable channels
— Dual-address transfer support with 8-, 16-, and 32-bit data capability, along with support for 16-byte (4×32-bit)
burst transfers
— Source/destination address pointers that can increment or remain constant
— 24-bit byte transfer counter per channel
— Auto-alignment transfers supported for efficient block movement
— Bursting and cycle-steal support
— Software-programmable DMA requests for the UARTs (3) and 32-bit timers (4)
— Channel linking support
•
Reset
— Separate reset in and reset out signals
— Seven sources of reset:
–
–
–
–
–
–
–
Power-on reset (POR)
External
Software
Watchdog
Loss of clock / loss of lock
Low-voltage detection (LVD)
JTAG
— Status flag indication of source of last reset
Chip configuration module (CCM)
•
•
— System configuration during reset
— Selects one of six clock modes
— Configures output pad drive strength
— Unique part identification number and part revision number
General purpose I/O interface
— Up to 56 bits of general purpose I/O on 100-pin package
— Up to 96 bits of general purpose I/O on 144-pin package
— Bit manipulation supported via set/clear functions
— Programmable drive strengths
— Unused peripheral pins may be used as extra GPIO
JTAG support for system level board testing
•
MCF52259 ColdFire Microcontroller, Rev. 0
Freescale Semiconductor
9
FREESCALE [ Freescale ]
