欢迎访问ic37.com |
会员登录 免费注册
发布采购

MCF52223CAF80 参数 Datasheet PDF下载

MCF52223CAF80图片预览
型号: MCF52223CAF80
PDF下载: 下载PDF文件 查看货源
内容描述: MCF52259的ColdFire微控制器 [MCF52259 ColdFire Microcontroller]
分类和应用: 微控制器
文件页数/大小: 50 页 / 1464 K
品牌: FREESCALE [ Freescale ]
 浏览型号MCF52223CAF80的Datasheet PDF文件第6页浏览型号MCF52223CAF80的Datasheet PDF文件第7页浏览型号MCF52223CAF80的Datasheet PDF文件第8页浏览型号MCF52223CAF80的Datasheet PDF文件第9页浏览型号MCF52223CAF80的Datasheet PDF文件第11页浏览型号MCF52223CAF80的Datasheet PDF文件第12页浏览型号MCF52223CAF80的Datasheet PDF文件第13页浏览型号MCF52223CAF80的Datasheet PDF文件第14页  
Family Configurations  
1.2.2  
V2 Core Overview  
The version 2 ColdFire processor core is comprised of two separate pipelines decoupled by an instruction buffer. The two-stage  
instruction fetch pipeline (IFP) is responsible for instruction-address generation and instruction fetch. The instruction buffer is  
a first-in-first-out (FIFO) buffer that holds prefetched instructions awaiting execution in the operand execution pipeline (OEP).  
The OEP includes two pipeline stages. The first stage decodes instructions and selects operands (DSOC); the second stage  
(AGEX) performs instruction execution and calculates operand effective addresses, if needed.  
The V2 core implements the ColdFire instruction set architecture revision A+ with support for a separate user stack pointer  
register and four new instructions to assist in bit processing. Additionally, the core includes the enhanced multiply-accumulate  
(EMAC) unit for improved signal processing capabilities. The EMAC implements a three-stage arithmetic pipeline, optimized  
for 32x32 bit operations, with support for four 48-bit accumulators. Supported operands include 16- and 32-bit signed and  
unsigned integers, signed fractional operands, and a complete set of instructions to process these data types. The EMAC  
provides support for execution of DSP operations within the context of a single processor at a minimal hardware cost.  
1.2.3  
Integrated Debug Module  
The ColdFire processor core debug interface is provided to support system debugging with low-cost debug and emulator  
development tools. Through a standard debug interface, access to debug information and real-time tracing capability is provided  
on 144-lead packages. This allows the processor and system to be debugged at full speed without the need for costly in-circuit  
emulators.  
The on-chip breakpoint resources include a total of nine programmable 32-bit registers: an address and an address mask register,  
a data and a data mask register, four PC registers, and one PC mask register. These registers can be accessed through the  
dedicated debug serial communication channel or from the processor’s supervisor mode programming model. The breakpoint  
registers can be configured to generate triggers by combining the address, data, and PC conditions in a variety of single- or  
dual-level definitions. The trigger event can be programmed to generate a processor halt or initiate a debug interrupt exception.  
This device implements revision B+ of the ColdFire Debug Architecture.  
The processor’s interrupt servicing options during emulator mode allow real-time critical interrupt service routines to be  
serviced while processing a debug interrupt event. This ensures the system continues to operate even during debugging.  
To support program trace, the V2 debug module provides processor status (PST[3:0]) and debug data (DDATA[3:0]) ports.  
These buses and the PSTCLK output provide execution status, captured operand data, and branch target addresses defining  
processor activity at the CPU’s clock rate. The device includes a new debug signal, ALLPST. This signal is the logical AND of  
the processor status (PST[3:0]) signals and is useful for detecting when the processor is in a halted state (PST[3:0] = 1111).  
The full debug/trace interface is available only on the 144-pin packages. However, every product features the dedicated debug  
serial communication channel (DSI, DSO, DSCLK) and the ALLPST signal.  
1.2.4  
JTAG  
The processor supports circuit board test strategies based on the Test Technology Committee of IEEE and the Joint Test Action  
Group (JTAG). The test logic includes a test access port (TAP) consisting of a 16-state controller, an instruction register, and  
three test registers (a 1-bit bypass register, a boundary-scan register, and a 32-bit ID register). The boundary scan register links  
the device’s pins into one shift register. Test logic, implemented using static logic design, is independent of the device system  
logic.  
The device implementation can:  
Perform boundary-scan operations to test circuit board electrical continuity  
Sample system pins during operation and transparently shift out the result in the boundary scan register  
Bypass the device for a given circuit board test by effectively reducing the boundary-scan register to a single bit  
Disable the output drive to pins during circuit-board testing  
Drive output pins to stable levels  
MCF52259 ColdFire Microcontroller, Rev. 0  
10  
Freescale Semiconductor