Pinout
VDD
PTA0
PTA1
24
23
22
21
20
19
1
2
3
4
5
6
7
8
EXTAL2
XTAL2
PTA2
BKGD/MS
PTA3
ADC0_SE18/TSI0_CH14
ADC0_SE17/TSI0_CH13
TSI0_CH10
ADC0_SE2
ADC0_SE3
VDDA
18
17
VSSA
IRQ/EZP_MS_b
Figure 23. 32-pin QFN
8.3 Module-by-module signals
NOTE
• On PTB0, EZP_MS_b is active only during reset. Refer to
the detailed boot description.
• PTC1 is open drain.
Table 38. Module signals by GPIO port and pin
64-pin
48-pin
44-pin
32-pin
Port
Module signal(s)
Power and ground
1
VDD
VDD
24
20
18
Table continues on the next page...
MCF51JU128 Data Sheet, Rev. 4, 01/2012.
Freescale Semiconductor, Inc.
61
FREESCALE [ Freescale ]
