Serial Communication Interface (S12SCIV5)
Module Base + 0x0007
7
6
5
4
3
2
1
0
R
W
R7
R6
R5
R4
R3
R2
R1
R0
T7
0
T6
0
T5
0
T4
0
T3
0
T2
0
T1
0
T0
0
Reset
Figure 11-13. SCI Data Registers (SCIDRL)
Read: Anytime; reading accesses SCI receive data register
Write: Anytime; writing accesses SCI transmit data register; writing to R8 has no effect
Table 11-13. SCIDRH and SCIDRL Field Descriptions
Field
Description
SCIDRH
Received Bit 8 — R8 is the ninth data bit received when the SCI is configured for 9-bit data format (M = 1).
Transmit Bit 8 — T8 is the ninth data bit transmitted when the SCI is configured for 9-bit data format (M = 1).
7
R8
SCIDRH
6
T8
SCIDRL
7:0
R7:R0 — Received bits seven through zero for 9-bit or 8-bit data formats
T7:T0 — Transmit bits seven through zero for 9-bit or 8-bit formats
R[7:0]
T[7:0]
NOTE
If the value of T8 is the same as in the previous transmission, T8 does not
have to be rewritten.The same value is transmitted until T8 is rewritten
In 8-bit data format, only SCI data register low (SCIDRL) needs to be
accessed.
When transmitting in 9-bit data format and using 8-bit write instructions,
write first to SCI data register high (SCIDRH), then SCIDRL.
11.4 Functional Description
This section provides a complete functional description of the SCI block, detailing the operation of the
design from the end user perspective in a number of subsections.
Figure 11-14 shows the structure of the SCI module. The SCI allows full duplex, asynchronous, serial
communication between the CPU and remote devices, including other CPUs. The SCI transmitter and
receiver operate independently, although they use the same baud rate generator. The CPU monitors the
status of the SCI, writes the data to be transmitted, and processes received data.
S12P-Family Reference Manual, Rev. 1.13
376
Freescale Semiconductor
FREESCALE [ Freescale ]
